/**
@page I2C_TwoBoards_RestartAdvComIT I2C Two Boards Restart Advanced Communication IT example
@verbatim
********************* COPYRIGHT(c) 2017 STMicroelectronics *******************
* @file I2C/I2C_TwoBoards_RestartAdvComIT/readme.txt
* @author MCD Application Team
* @version V1.8.0
* @date 21-April-2017
* @brief Description of the I2C_TwoBoards_RestartAdvComIT I2C example.
******************************************************************************
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
@endverbatim
@par Example Description
This example describes how to perform a multiple I2C data buffer transmission/reception
between two boards in Interrupt mode and with a restart condition.
Board: STM32L452RE-Nucleo Rev C (embeds a STM32L452RET6 device)
SCL Pin: PC0 (CN7, pin 38)
SDA Pin: PC1 (CN7, pin 36)
_________________________ _________________________
| ______________| |______________ |
| |I2C3 | | I2C3| |
| | | | | |
| | SCL |_____________________| SCL | |
| | | | | |
| | | | | |
| | | | | |
| | SDA |_____________________| SDA | |
| | | | | |
| |______________| |______________| |
| | | |
| GND|_____________________|GND |
|_STM32_Board 1___________| |_STM32_Board 2___________|
At the beginning of the main program the HAL_Init() function is called to reset
all the peripherals, initialize the Flash interface and the systick.
Then the SystemClock_Config() function is used to configure the system
clock (SYSCLK) to run at 80 MHz.
The I2C peripheral configuration is ensured by the HAL_I2C_Init() function.
This later is calling the HAL_I2C_MspInit()function which core is implementing
the configuration of the needed I2C resources according to the used hardware (CLOCK,
GPIO and NVIC). You may update this function to change I2C configuration.
The User push-button is used to initiate a communication between Master device to Slave.
User can initiate a new communication after each previous transfer completed.
The I2C communication is then initiated.
The project is splitted in two parts the Master Board and the Slave Board
- Master Board
The HAL_I2C_Master_Sequential_Transmit_IT() and the HAL_I2C_Master_Sequential_Receive_IT() functions
allow respectively the transmission and the reception of a predefined data buffer
in Master mode.
- Slave Board
The HAL_I2C_EnableListen_IT(), HAL_I2C_Slave_Sequential_Receive_IT() and the HAL_I2C_Slave_Sequential_Transmit_IT() functions
allow respectively the "Listen" the I2C bus for address match code event, reception and the transmission of a predefined data buffer
in Slave mode.
The user can choose between Master and Slave through "#define MASTER_BOARD"
in the "main.c" file.
If the Master board is used, the "#define MASTER_BOARD" must be uncommented.
If the Slave board is used the "#define MASTER_BOARD" must be commented.
Example execution:
On Master board side:
- Wait User push-button to be pressed.
This action initiate a write request by Master through HAL_I2C_Master_Sequential_Transmit_IT() or a write then read request
through HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Receive_IT() routine depends on Command Code type.
Initialy at power on Slave device through Interrupt "Listen" the I2C bus to perform an acknowledge of Match Address when necessary.
This "Listen" action is initiated by calling HAL_I2C_EnableListen_IT().
Command code type is decomposed in two categories :
1- Action Command code
a. Type of command which need an internal action from Slave Device without sending any specific answer to Master.
b. I2C sequence is composed like that :
_____________________________________________________________________________________
|_START_|_Slave_Address_|_Wr_|_A_|_Command_Code_BYTE_1_|_A_|_Command_Code_BYTE_2_|_A_|....
________________________________
|_Command_Code_BYTE_M_|_A_|_STOP_|
First of all, through HAL_I2C_Master_Sequential_Transmit_IT() routine, Master device generate an I2C start condition
with the Slave address and a write bit condition.
In Slave side, when address Slave match code is received on I2C3, an event interrupt (ADDR) occurs.
I2C3 IRQ Handler routine is then calling HAL_I2C_AddrCallback() which check Address Match Code and direction Write (Transmit)
to call the correct HAL_I2C_Slave_Sequential_Receive_IT() function.
This will allow Slave to enter in receiver mode and then acknowledge Master to send the Command code bytes through Interrupt.
The Command code data is received and treated byte per byte through HAL_I2C_SlaveRxCpltCallback() in Slave side until a STOP condition.
And so in Master side, each time the Slave acknowledge the byte received,
Master transfer the next data from flash memory buffer to I2C3 TXDR register until "Action Command code" Transfer completed.
Master auto-generate a Stop condition when transfer is achieved.
The STOP condition generate a STOP interrupt and initiate the end of reception on Slave side.
Thanks to HAL_I2C_ListenCpltCallback(), Slave is informed of the end of Communication with Master
and "Listen" mode is also terminated.
STM32L452RE-Nucleo Rev C board's LEDs can be used to monitor the transfer status :
Slave board side only :
- LED2 is turned ON when the reception process is completed.
Master board side only :
- LED2 is turned ON when the transmission process is completed.
Both side
- LED2 is slowly blinking (1 sec. period) when there is an error in communication process.(communication is stopped if any, using infinite loop)
These LEDs status are keeped a
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I2C.zip_HAL_LIB_i2c_联合开发 (270个子文件)
STM32L452RE_NUCLEO.axf 792KB
STM32L452RE_NUCLEO.axf 790KB
main.c 23KB
main.c 21KB
main.c 18KB
main.c 17KB
main.c 16KB
main.c 16KB
system_stm32l4xx.c 14KB
system_stm32l4xx.c 14KB
system_stm32l4xx.c 14KB
system_stm32l4xx.c 14KB
system_stm32l4xx.c 14KB
system_stm32l4xx.c 14KB
system_stm32l4xx.c 14KB
main.c 13KB
stm32l4xx_hal_msp.c 8KB
stm32l4xx_it.c 7KB
stm32l4xx_it.c 6KB
stm32l4xx_it.c 6KB
stm32l4xx_it.c 6KB
stm32l4xx_it.c 6KB
stm32l4xx_it.c 6KB
stm32l4xx_hal_msp.c 6KB
stm32l4xx_hal_msp.c 6KB
stm32l4xx_hal_msp.c 6KB
stm32l4xx_hal_msp.c 6KB
stm32l4xx_hal_msp.c 6KB
stm32l4xx_it.c 5KB
stm32l4xx_hal_msp.c 5KB
Serial.c 2KB
Retarget.c 1KB
.cproject 21KB
.cproject 21KB
.cproject 21KB
.cproject 21KB
.cproject 21KB
.cproject 21KB
.cproject 21KB
stm32l4xx_hal_i2c.crf 831KB
stm32l4xx_hal_i2c.crf 831KB
stm32l4xx_hal_rcc_ex.crf 813KB
stm32l4xx_hal_rcc_ex.crf 813KB
stm32l4xx_hal_uart.crf 810KB
stm32l4xx_hal_uart.crf 810KB
stm32l4xx_hal_rcc.crf 805KB
stm32l4xx_hal_rcc.crf 805KB
stm32l4xx_hal_pwr_ex.crf 797KB
stm32l4xx_hal_pwr_ex.crf 797KB
stm32l4xx_hal_dma.crf 796KB
stm32l4xx_hal_dma.crf 796KB
main.crf 796KB
main.crf 795KB
stm32l4xx_hal_msp.crf 795KB
stm32l4xx_hal_msp.crf 795KB
stm32l4xx_nucleo.crf 795KB
stm32l4xx_nucleo.crf 795KB
stm32l4xx_it.crf 794KB
stm32l4xx_it.crf 794KB
stm32l4xx_hal_gpio.crf 793KB
stm32l4xx_hal_gpio.crf 793KB
stm32l4xx_hal.crf 792KB
stm32l4xx_hal.crf 792KB
stm32l4xx_hal_pwr.crf 791KB
stm32l4xx_hal_pwr.crf 791KB
stm32l4xx_hal_uart_ex.crf 791KB
stm32l4xx_hal_uart_ex.crf 791KB
stm32l4xx_hal_i2c_ex.crf 791KB
stm32l4xx_hal_i2c_ex.crf 791KB
stm32l4xx_hal_cortex.crf 790KB
stm32l4xx_hal_cortex.crf 790KB
system_stm32l4xx.crf 790KB
system_stm32l4xx.crf 790KB
stm32l4xx_hal_uart_ex.d 3KB
stm32l4xx_hal_uart_ex.d 3KB
stm32l4xx_hal_msp.d 3KB
stm32l4xx_hal_msp.d 3KB
stm32l4xx_hal_pwr_ex.d 3KB
stm32l4xx_hal_rcc_ex.d 3KB
stm32l4xx_hal_i2c_ex.d 3KB
stm32l4xx_hal_rcc_ex.d 3KB
stm32l4xx_hal_i2c_ex.d 3KB
stm32l4xx_hal_pwr_ex.d 3KB
stm32l4xx_hal_cortex.d 3KB
stm32l4xx_hal_cortex.d 3KB
stm32l4xx_nucleo.d 3KB
stm32l4xx_nucleo.d 3KB
stm32l4xx_hal_gpio.d 3KB
stm32l4xx_hal_uart.d 3KB
stm32l4xx_hal_gpio.d 3KB
stm32l4xx_hal_uart.d 3KB
stm32l4xx_it.d 3KB
stm32l4xx_it.d 3KB
stm32l4xx_hal_rcc.d 3KB
stm32l4xx_hal_dma.d 3KB
stm32l4xx_hal_i2c.d 3KB
stm32l4xx_hal_pwr.d 3KB
stm32l4xx_hal_dma.d 3KB
stm32l4xx_hal_rcc.d 3KB
stm32l4xx_hal_pwr.d 3KB
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