dispc-compat.rar_V2

/* * Copyright (C) 2012 Texas Instruments * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 as published by * the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program. If not, see <http://www.gnu.org/licenses/>. */ #define DSS_SUBSYS_NAME "APPLY" #include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/jiffies.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/seq_file.h> #include <video/omapdss.h> #include "dss.h" #include "dss_features.h" #include "dispc-compat.h" #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ DISPC_IRQ_OCP_ERR | \ DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ DISPC_IRQ_SYNC_LOST | \ DISPC_IRQ_SYNC_LOST_DIGIT) #define DISPC_MAX_NR_ISRS 8 struct omap_dispc_isr_data { omap_dispc_isr_t isr; void *arg; u32 mask; }; struct dispc_irq_stats { unsigned long last_reset; unsigned irq_count; unsigned irqs[32]; }; static struct { spinlock_t irq_lock; u32 irq_error_mask; struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; u32 error_irqs; struct work_struct error_work; #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS spinlock_t irq_stats_lock; struct dispc_irq_stats irq_stats; #endif } dispc_compat; #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS static void dispc_dump_irqs(struct seq_file *s) { unsigned long flags; struct dispc_irq_stats stats; spin_lock_irqsave(&dispc_compat.irq_stats_lock, flags); stats = dispc_compat.irq_stats; memset(&dispc_compat.irq_stats, 0, sizeof(dispc_compat.irq_stats)); dispc_compat.irq_stats.last_reset = jiffies; spin_unlock_irqrestore(&dispc_compat.irq_stats_lock, flags); seq_printf(s, "period %u ms\n", jiffies_to_msecs(jiffies - stats.last_reset)); seq_printf(s, "irqs %d\n", stats.irq_count); #define PIS(x) \ seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]); PIS(FRAMEDONE); PIS(VSYNC); PIS(EVSYNC_EVEN); PIS(EVSYNC_ODD); PIS(ACBIAS_COUNT_STAT); PIS(PROG_LINE_NUM); PIS(GFX_FIFO_UNDERFLOW); PIS(GFX_END_WIN); PIS(PAL_GAMMA_MASK); PIS(OCP_ERR); PIS(VID1_FIFO_UNDERFLOW); PIS(VID1_END_WIN); PIS(VID2_FIFO_UNDERFLOW); PIS(VID2_END_WIN); if (dss_feat_get_num_ovls() > 3) { PIS(VID3_FIFO_UNDERFLOW); PIS(VID3_END_WIN); } PIS(SYNC_LOST); PIS(SYNC_LOST_DIGIT); PIS(WAKEUP); if (dss_has_feature(FEAT_MGR_LCD2)) { PIS(FRAMEDONE2); PIS(VSYNC2); PIS(ACBIAS_COUNT_STAT2); PIS(SYNC_LOST2); } if (dss_has_feature(FEAT_MGR_LCD3)) { PIS(FRAMEDONE3); PIS(VSYNC3); PIS(ACBIAS_COUNT_STAT3); PIS(SYNC_LOST3); } #undef PIS } #endif /* dispc.irq_lock has to be locked by the caller */ static void _omap_dispc_set_irqs(void) { u32 mask; int i; struct omap_dispc_isr_data *isr_data; mask = dispc_compat.irq_error_mask; for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { isr_data = &dispc_compat.registered_isr[i]; if (isr_data->isr == NULL) continue; mask |= isr_data->mask; } dispc_write_irqenable(mask); } int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) { int i; int ret; unsigned long flags; struct omap_dispc_isr_data *isr_data; if (isr == NULL) return -EINVAL; spin_lock_irqsave(&dispc_compat.irq_lock, flags); /* check for duplicate entry */ for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { isr_data = &dispc_compat.registered_isr[i]; if (isr_data->isr == isr && isr_data->arg == arg && isr_data->mask == mask) { ret = -EINVAL; goto err; } } isr_data = NULL; ret = -EBUSY; for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { isr_data = &dispc_compat.registered_isr[i]; if (isr_data->isr != NULL) continue; isr_data->isr = isr; isr_data->arg = arg; isr_data->mask = mask; ret = 0; break; } if (ret) goto err; _omap_dispc_set_irqs(); spin_unlock_irqrestore(&dispc_compat.irq_lock, flags); return 0; err: spin_unlock_irqrestore(&dispc_compat.irq_lock, flags); return ret; } EXPORT_SYMBOL(omap_dispc_register_isr); int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) { int i; unsigned long flags; int ret = -EINVAL; struct omap_dispc_isr_data *isr_data; spin_lock_irqsave(&dispc_compat.irq_lock, flags); for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { isr_data = &dispc_compat.registered_isr[i]; if (isr_data->isr != isr || isr_data->arg != arg || isr_data->mask != mask) continue; /* found the correct isr */ isr_data->isr = NULL; isr_data->arg = NULL; isr_data->mask = 0; ret = 0; break; } if (ret == 0) _omap_dispc_set_irqs(); spin_unlock_irqrestore(&dispc_compat.irq_lock, flags); return ret; } EXPORT_SYMBOL(omap_dispc_unregister_isr); static void print_irq_status(u32 status) { if ((status & dispc_compat.irq_error_mask) == 0) return; #define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : "" pr_debug("DISPC IRQ: 0x%x: %s%s%s%s%s%s%s%s%s\n", status, PIS(OCP_ERR), PIS(GFX_FIFO_UNDERFLOW), PIS(VID1_FIFO_UNDERFLOW), PIS(VID2_FIFO_UNDERFLOW), dss_feat_get_num_ovls() > 3 ? PIS(VID3_FIFO_UNDERFLOW) : "", PIS(SYNC_LOST), PIS(SYNC_LOST_DIGIT), dss_has_feature(FEAT_MGR_LCD2) ? PIS(SYNC_LOST2) : "", dss_has_feature(FEAT_MGR_LCD3) ? PIS(SYNC_LOST3) : ""); #undef PIS } /* Called from dss.c. Note that we don't touch clocks here, * but we presume they are on because we got an IRQ. However, * an irq handler may turn the clocks off, so we may not have * clock later in the function. */ static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) { int i; u32 irqstatus, irqenable; u32 handledirqs = 0; u32 unhandled_errors; struct omap_dispc_isr_data *isr_data; struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; spin_lock(&dispc_compat.irq_lock); irqstatus = dispc_read_irqstatus(); irqenable = dispc_read_irqenable(); /* IRQ is not for us */ if (!(irqstatus & irqenable)) { spin_unlock(&dispc_compat.irq_lock); return IRQ_NONE; } #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS spin_lock(&dispc_compat.irq_stats_lock); dispc_compat.irq_stats.irq_count++; dss_collect_irq_stats(irqstatus, dispc_compat.irq_stats.irqs); spin_unlock(&dispc_compat.irq_stats_lock); #endif print_irq_status(irqstatus); /* Ack the interrupt. Do it here before clocks are possibly turned * off */ dispc_clear_irqstatus(irqstatus); /* flush posted write */ dispc_read_irqstatus(); /* make a copy and unlock, so that isrs can unregister * themselves */ memcpy(registered_isr, dispc_compat.registered_isr, sizeof(registered_isr)); spin_unlock(&dispc_compat.irq_lock); for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { isr_data = &registered_isr[i]; if (!isr_data->isr) continue; if (isr_data->mask & irqstatus) { isr_data->isr(isr_data->arg, irqstatus); handledirqs |= isr_data->mask; } } spin_lock(&dispc_compat.irq_lock); unhandled_errors = irqstatus & ~handledirqs & dispc_compat.irq_error_mask; if (unhandled_errors) { dispc_compat.error_irqs |= unhandled_errors; dispc_compat.irq_error_mask &= ~unhandled_errors; _omap_dispc_set_irqs(); schedule_work(&dispc_compat.error_work); } spin_unlock(&dispc_compat.irq_lock); return IRQ_HANDLED; } static void dispc_error_worker(struct work_struct *work) { int i; u32 errors; unsigned long flags; static const unsigned fifo_underflow_bits[] = { DISPC_IRQ_GFX_FIFO_UNDERFLOW, DISPC_IRQ_VID1_FIFO_UNDERFLOW, DISPC_IRQ_VID2_FIFO_UNDERFLOW, DISPC_IRQ_VID3_FIFO_UNDERFLOW, }; spin_lock_irqsave(&dispc_compat.irq_lock, flags);