<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xillybus</spirit:vendor>
<spirit:library>xillybus</spirit:library>
<spirit:name>xillybus_ip</spirit:name>
<spirit:version>1.0</spirit:version>
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<spirit:busInterface>
<spirit:name>S_AXI</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
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<spirit:name>AWADDR</spirit:name>
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<spirit:name>S_AXI_AWADDR</spirit:name>
</spirit:physicalPort>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
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<spirit:physicalPort>
<spirit:name>S_AXI_AWVALID</spirit:name>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
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<spirit:name>S_AXI_AWREADY</spirit:name>
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<spirit:portMap>
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<spirit:name>WDATA</spirit:name>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
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<spirit:physicalPort>
<spirit:name>S_AXI_WSTRB</spirit:name>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
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<spirit:physicalPort>
<spirit:name>S_AXI_WVALID</spirit:name>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
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<spirit:portMap>
<spirit:logicalPort>
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<spirit:name>S_AXI_BVALID</spirit:name>
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<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
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<spirit:physicalPort>
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<spirit:portMap>
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<spirit:portMap>
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<spirit:name>ARREADY</spirit:name>
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<spirit:name>S_AXI_ARREADY</spirit:name>
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<spirit:portMap>
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<spirit:name>RDATA</spirit:name>
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<spirit:physicalPort>
<spirit:name>S_AXI_RDATA</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RRESP</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_RVALID</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
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<spirit:physicalPort>
<spirit:name>S_AXI_RREADY</spirit:name>
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</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>m_axi</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:master>
<spirit:addressSpaceRef spirit:addressSpaceRef="m_axi"/>
</spirit:master>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_axi_awaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWLEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_axi_awlen</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWSIZE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_axi_awsize</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWBURST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_axi_awburst</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWCACHE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_axi_awcache</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWPROT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>m_axi_awprot</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
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<spirit:physicalPort>
<spirit:name>m_axi_awvalid</spirit:name>
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</spirit:port
xillinux-eval-zedboard-2.0c.zip_GPS_grasspzo_iran
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xillinux-eval-zedboard-2.0c.zip （70个子文件） 
xillinux-eval-zedboard-2.0c runonce 
vga_fifo.xco 7KB fifo_8x2048.xco 7KB runonce.xise 35KB fifo_32x512.xco 7KB vhdl xillydemo.xise 37KB src xillybus_core.v 3KB fifo_8x2048.v 233B xillydemo.vhd 18KB fifo_32x512.v 234B xillybus.v 14KB i2s_audio.v 4KB smbus.v 5KB xillydemo.ucf 6KB system.v 6KB xillydemo-vivado.tcl 6KB cores xillybus_core.ngc 1.69MB xillyvga_core.ngc 316KB blockdesign xillybus_block xgui xpgui.tcl 181B xci fifo_xillybus_fwft_8 fifo_xillybus_fwft_8.xci 51KB fifo_xillybus_32 fifo_xillybus_32.xci 51KB fifo_xillybus_fwft_32 fifo_xillybus_fwft_32.xci 51KB fifo_xillybus_8 fifo_xillybus_8.xci 51KB src xillybus_core.v 3KB xillybus_block.v 16KB component.xml 90KB src detach_clocks.xdc 376B i2s_audio_axis.v 3KB xillydemo.v 6KB smbus_axis.v 5KB xillydemo-vivado.tcl 7KB vivado_system vivado_system.bd 72KB bootfiles devicetree.dtb 9KB boot.bin 339KB system system.mhs 17KB pcores xillyvga_v1_00_a hdl verilog xillyvga.v 4KB xillyvga_core.v 1KB data xillyvga_v2_1_0.pao 82B xillyvga_v2_1_0.mpd 6KB xillybus_v1_00_a hdl verilog xillybus.v 7KB data xillybus_v2_1_0.mpd 8KB xillybus_v2_1_0.pao 38B xillybus_lite_v1_00_a data xillybus_lite_v2_1_0.bbd 24B xillybus_lite_v2_1_0.mpd 4KB netlist xillybus_lite.ngc 58KB data ps7_system_prj.xml 14KB system.xmp 610B verilog xillydemo.xise 37KB src xillybus_core.v 3KB fifo_8x2048.v 233B fifo_32x512.v 234B xillybus.v 14KB xillydemo.v 9KB i2s_audio.v 4KB smbus.v 5KB xillydemo.ucf 6KB system.v 6KB xillydemo-vivado.tcl 6KB vivado-essentials fifo_8x2048 fifo_8x2048.xci 51KB showstopper.tcl 2KB vga_fifo vga_fifo.xci 51KB fifo_32x512 fifo_32x512.xci 51KB vivado_system vivado_system.bd 62KB vivado-ip xillyvga xillyvga.srcs sources_1 imports verilog xillyvga.v 3KB xillyvga_core.v 1KB component.xml 67KB xillybus_lite component.xml 29KB xillybus_ip xillybus.srcs sources_1 imports verilog xillybus_ip.v 6KB component.xml 113KB xillydemo.xdc 8KB system.v 8KB资源评论
