mcbsp.rar_CHIP SUPPORT LIBRARY_MCBSP_McBSP配置

/* * Copyright (C) 2003 Texas Instruments Incorporated * All Rights Reserved */ /* *---------main_mcbsp1.c--------- * * mcbsp1 Example configures the serial port for digital loopback mode. * We then use the CPU to write/read from the port. In loopback mode, we * should read back the same value as written, which is checked for in a loop */ #include <stdio.h> #include <csl.h> #include <csl_mcbsp.h> /* create a config structure for digital loopback mode */ static MCBSP_Config ConfigLoopback = { /* Serial Port Control Register (SPCR) */ MCBSP_SPCR_RMK( MCBSP_SPCR_FREE_YES, /* Serial clock free running mode(FREE) MCBSP_SPCR_FREE_NO - During emulation halt,SOFT bit determines operation of McBSP. MCBSP_SPCR_FREE_YES - During emulation halt, serial clocks continue to run. */ MCBSP_SPCR_SOFT_YES, /* Serial clock emulation mode(SOFT) MCBSP_SPCR_SOFT_NO - In conjunction with FREE = 0, serial port clock stops immediately during emulation halt,thus aborting any transmissions. MCBSP_SPCR_SOFT_YES - In conjunction with FREE = 0, during emulation halt, serial port clock stops after completion of current transmission. */ MCBSP_SPCR_FRST_YES, /* Frame sync generator reset(FRST) MCBSP_SPCR_FRST_YES /MCBSP_SPCR_FRST_0 - Frame sync generation logic is reset. MCBSP_SPCR_FRST_NO /MCBSP_SPCR_FRST_1 - Frame sync signal is generated after eight CLKG clocks. */ MCBSP_SPCR_GRST_YES, /* Sample rate generator reset(GRST) MCBSP_SPCR_GRST_YES /MCBSP_SPCR_GRST_0 - Reset MCBSP_SPCR_GRST_NO /MCBSP_SPCR_GRST_1 -Out of reset*/ MCBSP_SPCR_XINTM_XRDY,/* Transmit interrupt mode(XINTM) MCBSP_SPCR_XINTM_XRDY - XINT driven by XRDY MCBSP_SPCR_XINTM_EOS - XINT generated by end-of-subframe in multichannel operation MCBSP_SPCR_XINTM_FRM - XINT generated by a new frame synchronization MCBSP_SPCR_XINTM_XSYNCERR - XINT generated by XSYNCERR */ MCBSP_SPCR_XSYNCERR_NO,/* Transmit synchronization error MCBSP_SPCR_XSYNCERR_NO /MCBSP_SPCR_XSYNCERR_0 - No frame synchronization error MCBSP_SPCR_XSYNCERR_YES /MCBSP_SPCR_XSYNCERR_1 - Frame synchronization error detected by McBSP */ MCBSP_SPCR_XRST_YES, /* Transmitter reset(XRST). This resets or enables transmitter. MCBSP_SPCR_XRST_YES /MCBSP_SPCR_XRST_0 - Serial port transmitter is disabled and is in reset state. MCBSP_SPCR_XRST_NO /MCBSP_SPCR_XRST_1 - Serial port transmitter is enabled. */ MCBSP_SPCR_DLB_ON, /* Digital loopback(DLB) mode MCBSP_SPCR_DLB_OFF - DLB Disabled MCBSP_SPCR_DLB_ON - DLB Enabled */ MCBSP_SPCR_RJUST_RZF,/*Receive data sign-extension and justification mode(RJUST) MCBSP_SPCR_RJUST_RZF - Right-justify and zero-fill MSBs in DRR. MCBSP_SPCR_RJUST_RSE - Right-justify and sign-extend MSBs in DRR. MCBSP_SPCR_RJUST_LZF - Left-justify and zero-fill LSBs in DRR. */ MCBSP_SPCR_CLKSTP_DISABLE,/* Clock stop(CLKSTP) mode MCBSP_SPCR_CLKSTP_DISABLE - Disabled. Normal clocking enabled for non-SPI mode. MCBSP_SPCR_CLKSTP_NODELAY -Clock starts without delay. MCBSP_SPCR_CLKSTP_DELAY - Clock starts with delay.*/ MCBSP_SPCR_DXENA_OFF,/* DX Enabler(DXENA) -Extra delay for DX turn-on time. Only first bit of data is delayed. MCBSP_SPCR_DXENA_OFF - DX enabler is off. MCBSP_SPCR_DXENA_ON - DX enabler is on. */ MCBSP_SPCR_RINTM_RRDY,/* Receive interrupt(RINT) mode MCBSP_SPCR_RINTM_RRDY - RINT driven by RRDY MCBSP_SPCR_RINTM_EOS - RINT generated by end-of-subframe in multichannel operation MCBSP_SPCR_RINTM_FRM - RINT generated by a new frame synchronization MCBSP_SPCR_RINTM_RSYNCERR -RINT generated by RSYNCERR*/ MCBSP_SPCR_RSYNCERR_NO,/* Receive synchronization error(RSYNCERR) MCBSP_SPCR_RSYNCERR_NO /MCBSP_SPCR_RSYNCERR_0 - No frame synchronization error MCBSP_SPCR_RSYNCERR_YES /MCBSP_SPCR_RSYNCERR_1 - Frame synchronization error detected by McBSP */ MCBSP_SPCR_RRST_YES /* Receiver reset(RRST). This resets or enables receiver. MCBSP_SPCR_RRST_YES /MCBSP_SPCR_RRST_0 - Serial port receiver is disabled and is in reset state. MCBSP_SPCR_RRST_NO /MCBSP_SPCR_RRST_1 - Serial port receiver is enabled. */ ), /* Receive Control Register (RCR) */ MCBSP_RCR_RMK( MCBSP_RCR_RPHASE_SINGLE, /* Receive phases MCBSP_RCR_RPHASE_SINGLE - Single phase frame MCBSP_RCR_RPHASE_DUAL - Dual phase frame */ MCBSP_RCR_RFRLEN2_OF(0), /* Receive frame length in phase 2(RFRLEN2) 000 0000b: 1 word per phase 000 0001b: 2 words per phase . . . . . . . . . . . . 111 1111b: 128 words per phase */ MCBSP_RCR_RWDLEN2_8BIT,/* Receive element length in phase 2(RWDLEN2) MCBSP_RCR_RWDLEN2_8BIT - 8 bits MCBSP_RCR_RWDLEN2_12BIT - 12 bits MCBSP_RCR_RWDLEN2_16BIT - 16 bits MCBSP_RCR_RWDLEN2_20BIT - 20 bits MCBSP_RCR_RWDLEN2_24BIT - 24 bits MCBSP_RCR_RWDLEN2_32BIT - 32 bits */ MCBSP_RCR_RCOMPAND_MSB,/* Receive companding mode (RCOMPAND) MCBSP_RCR_RCOMPAND_MSB - No companding.Data transfer sta