tlv5619.rar_TLV5619资源-CSDN文库

共20个文件

ewd：2个

ewp：2个

r43：2个

版权申诉

79 浏览量 2022-09-19 20:01:49 上传评论收藏 690KB RAR 举报

资源推荐

资源详情

资源评论

收起资源包目录

tlv5619.rar （20个子文件）

驱动程序

tlv5619.ewp 51KB

main.c 2KB

tlv5619.eww 161B

tlv5619.h 182B

tlv5619.c 1KB

Backup of tlv5619.ewp 49KB

tlv5619.ewd 20KB

tlv5619.dep 2KB

settings

tlv5619.dbgdt 5KB

tlv5619.dni 1KB

tlv5619.wsdt 3KB

tlv5619.cspy.bat 2KB

tlv5619CustomSfr.sfr 25B

Backup of tlv5619.ewd 20KB

Debug

List

Exe

tlv5619.d43 22KB

Obj

tlv5619.r43 10KB

main.r43 12KB

path.txt 0B

dac55731.pdf 441KB

tlv5619.pdf 479KB

www.ti.com

FEATURES DESCRIPTION

APPLICATIONS

D10

D11

LDAC

GND

OUT

REFIN

DW OR PW PACKAGE

(TOP VIEW)

TLV5619

SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER

WITH POWER DOWN

• Single Supply 2.7-V to 5.5-V Operation

The TLV5619 is a 12-bit voltage output DAC with a

microprocessor and TMS320 compatible parallel

• ± 0.4 LSB Differential Nonlinearity (DNL),

interface. The 12 data bits are double buffered so that

±1.5 LSB Integral Nonlinearity (INL)

the output can be updated asynchronously using the

• 12-Bit Parallel Interface

LDAC pin. During normal operation, the device dissi-

• Compatible With TMS320 DSP

pates 8 mW at a 5-V supply and 4.3 mW at a 3-V

supply. The power consumption can be lowered to 50

• Internal Power On Reset

nW by setting the DAC to power-down mode.

• Settling Time 1 µs Typ

The output voltage is buffered by a ×2 gain rail-to-rail

• Low Power Consumption:

amplifier, which features a Class A output stage to

– 8 mW for 5-V Supply

improve stability and reduce settling time.

– 4.3 mW for 3-V Supply

• Reference Input Buffers

• Voltage Output

• Monotonic Over Temperature

• Asynchronous Update

• Battery Powered Test Instruments

• Digital Offset and Gain Adjustment

• Battery Operated/Remote Industrial Controls

• Machine and Motion Control Devices

• Cordless and Wireless Telephones

• Speech Synthesis

AVAILABLE OPTIONS

• Communication Modulators

• Arbitrary Waveform Generation

PACKAGE

SMALL

TSSOP (PW)

OUTLINE (DW)

0°C to 70°C TLV5619CDW TLV5619CPW

40°C to 85°C TLV5619IDW TLV5619IPW

40°C to 125°C TLV5619QDW —

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

www.ti.com

REFIN

Power-On

Reset

LDAC

OUT

12-Bit

Input

Select

and

Control

Logic

12-Bit

DAC

Latch

D10

D11

Resistor

String DAC

TLV5619

SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

Terminal Functions

TERMINAL

I/O DESCRIPTION

NAME NO.

CS 18 I Chip select

D0 (LSB)-D11 (MSB) 19, 20, 1-10 I Parallel data input

GND 14 Ground

LDAC 16 I Load DAC

OUT 13 O Analog output

PD 15 I When low, disables all buffer amplifier voltages to reduce supply current

REFIN 12 I Voltage reference input

11 Positive power supply

WE 17 I Write enable

www.ti.com

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

TLV5619

SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

Supply voltage (V

to GND) 7 V

Analog input voltage range - 0.3 V to V

+ 0.3 V

Reference input voltage V

+ 0.3 V

Digital input voltage range to GND - 0.3 V to V

+ 0.3 V

Operating free-air temperature range, T

TLV5619C 0°C to 70°C

TLV5619I -40°C to 85°C

TLV5619Q -40°C to 125°C

Storage temperature range, T

stg

-65°C to 150°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under, , absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under, , recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

MIN NOM MAX UNIT

Supply voltage, V

(5-V Supply) 4.5 5 5.5 V

Supply voltage, V

(3-V Supply) 2.7 3 3.3 V

= 2.7 V 2

High-level digital input voltage, V

= 5.5 V 2.4

= 2.7 V 0.6

Low-level digital input voltage, V

TLV5619C and TLV5619I 1

= 5.5 V

TLV5619Q 0.8

Reference voltage, V

ref

to REFIN terminal (5-V Supply) 0 2.048 V

-1.5 V

Reference voltage, V

ref

to REFIN terminal (3-V Supply) 0 1.024 V

-1.5 V

Load resistance, R

2 10 kΩ

Load capacitance, C

100 pF

TLV5619C 0 70

Operating free-air temperature, T

TLV5619I 40 85 °C

TLV5619Q 40 125

www.ti.com

ELECTRICAL CHARACTERISTICS

TLV5619

SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004

over recommended operating free-air temperature range, sdupply voltages, and reference voltages (unless otherwise noted)

STATIC DAC SPECIFICATIONS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution V

ref(REFIN)

= 2.048 V at 5 V, 1.024 V at 3 V 12 bits

ref(REFIN)

= 2.048 V at 5 V,

Integral nonlinearity (INL) See

(1)

±1.5 ±4 LSB

1.024 V at 3 V,

ref(REFIN)

= 2.048 V at 5 V,

Differential nonlinearity (DNL) See

(2)

±0.4 ±1 LSB

1.024 V at 3 V,

ref(REFIN)

= 2.048 V at 5 V,

Zero-scale error (offset error at zero scale) See

(3)

±3 ±20 mV

1.024 V at 3 V,

ref(REFIN)

= 2.048 V at 5 V,

Zero-scale-error temperature coefficient See

(4)

3 ppm/°C

1.024 V at 3 V,

ref(REFIN)

= 2.048 V at 5 V, % of FS

Gain error See

(5)

±0.25 ±0.5

1.024 V at 3 V, voltage

ref(REFIN)

= 2.048 V at 5 V,

Gain error temperature coefficient See

(6)

1 ppm/°C

1.024 V at 3 V,

Zero scale 65

PSRR Power-supply rejection ratio See

(7)

and

(8)

Gain 65

(1) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from

the line between zero and full scale excluding the effects of zero code and full-scale errors.

(2) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB

amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)

as a change in the digital input code.

(3) Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

(4) Zero-scale-error temperature coefficient is given by: E

TC = [E

max

) - E

min

)]/V

ref

× 10

/(T

max

- T

min

(5) Gain error is the deviation from the ideal output (2 × V

ref

- 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

(6) Gain temperature coefficient is given by: E

TC = [E

max

) - E

min

)]/V

ref

× 10

/(T

max

- T

min

(7) Zero-scale-error rejection ratio (EZS-RR) is measured by varying the V

from 4.5 V to 5.5 V dc and measuring the proportion of this

signal imposed on the zero-code output voltage.

(8) Gain-error rejection ratio (EG-RR) is measured by varying the V

from 4.5 V to 5.5 V dc and measuring the proportion of this signal

imposed on the full-scale output voltage after subtracting the zero scale change.

OUTPUT SPECIFICATIONS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Voltage output range R

= 10 kΩ 0 V

-0.4 V

% of FS

Output load regulation accuracy V

O(OUT)

= 4.096 V, 2.048 V R

= 2 kΩ 0.1 0.29

voltage

5-V Supply 100

O(OUT)

= 0 V, Full scale

OSC(source)

Output short circuit source current mA

code

3-V Supply 25

5-V Supply 10

O(source)

Output source current R

= 100Ω mA

3-V Supply 10

www.ti.com

TIMING REQUIREMENTS

TLV5619

SLAS172F – DECEMBER 1997 – REVISED FEBRUARY 2004

REFERENCE INPUT (REFIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ref

Reference input voltage See

(1)

0 V

-1.5 V

Reference input resistance 10 MΩ

Reference input capacitance 5 pF

Reference feed through REFIN = 1 V

at 1 kHz + 1.024 V dc (see

(2)

) 60 dB

Reference input bandwidth REFIN = 0.2 V

+ 1.024 V dc at -3 dB 1.4 MHz

DIGITAL INPUTS (D0-D11, CS, WE, LDAC, PD)

High-level digital input current V

= V

1 µA

Low-level digital input current V

= 0 V 1 µA

Input capacitance 8 pF

(1) Reference input voltages greater than V

/2 will cause output saturation for large DAC codes.

(2) Reference feedthrough is measured at the DAC output with an input code = 0x000 and a V

ref(REFIN)

input = 1.024 V dc + 1 V

1 kHz.

POWER SUPPLY

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

5-V Supply 1.6 3

Power supply current No load, All inputs 0 V or V

3-V Supply 1.44 2.7

Power down supply current 0.01 10 µA

ANALOG OUTPUT DYNAMIC PERFORMANCE

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

5-V

ref(REFIN)

= 2.048 V,

8 12 V/µs

Supply

= 100 pF, V

ref(REFIN)

=1.024 V,

SR Slew rate

= 10 kΩ V

from 10% to 90%

3-V

6 9 V/µs

from 90% to 10%

Supply

Output settling time (full

To ±0.5 LSB, R

= 10 kΩ, C

= 100 pF, See

(1)

1 3 µs

scale)

Glitch energy DIN = all 0s to all 1s 5 nV-s

= 480 kSPS, BW = 20 kHz, C

= 100 pF, 5-V

S/N Signal to noise 65 78

OUT

= 1 kHz, R

= 10 kΩ , T

= 25°C, See

(2)

Supply

5-V

58 67

Supply

= 480 kSPS, BW = 20 kHz, C

= 100 pF,

S/(N+D) Signal to noise + distortion

OUT

= 1 kHz, R

= 10 kΩ, T

= 25°C, See

(2)

3-V

58 69 dB

Supply

= 480 kSPS, BW = 20 kHz, C

= 100 pF,

Total harmonic distortion 68 60

OUT

= 1 kHz, R

= 10 kΩ, T

= 25°C, See

(2)

Spurious free dynamic f

= 480 kSPS, BW = 20 kHz, C

= 100 pF,

60 72

range f

OUT

= 1 kHz, R

= 10 kΩ, T

= 25°C, See

(2)

(1) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 32

to 4063 or 4063 to 32. Limits are ensured by design and characterization, but are not production tested.

(2) 1 kHz sinewave generated by DAC, reference voltage = 1.024 V at 3 V and 2.048 V at 5 V.

DIGITAL INPUTS

MIN NOM MAX UNIT

su(CS-WE)

Setup time, CS low before positive WE edge 13 ns

su(D)

Setup time, data ready before positive WE edge 9 ns

h(D)

Hold time, data held after positive WE edge 0 ns

su(WE-LD)

Setup time, positive WE edge before LDAC low 0 ns

wh(WE)

Pulse width, WE high 25 ns

w(LD)

Pulse width, LDAC low 25 ns

评论收藏

内容反馈

版权申诉

小贝德罗

粉丝: 71
资源: 1万+

tlv5619.rar_TLV5619

tlv5619.rar_TLV5619_avr da

TLV5619.rar_TLV5619_tlv5619应用电路

tlv5619.zip_TLV5619

DAC_TLV5616.rar_DAC tlv5619 verilog_fpga TLV5616_tlv5616 FPGA_t

tlv.rar_conversion_tlv

tlv5620.rar_TLV5620_TLV5620驱动

TLV5638控制程序.rar_STM32 外部DA_TLV5638_TLV5638用法_TV5638_实现DA转换

TLV5638.rar_ MSP430 tlv5638_TLV5638_msp430 TLV5638_tlv56_tlv5638

TLV320AIC31_test.rar_TLV320AIC31_TLV320AIC31_test_TLV320AIC31_te

TLV5618.rar for msp430

TLV5638-.rar_DA TLV5638_TLV5638_avr da _tlv5638 AVR

TLV2544.rar_TLV2544_tlv2544程序

TLV320AIC31_driver.rar_ EM770W_TLV320AIC31_codec_tlv320_tlv320ai

tlv5638.rar_TLV5638_TLV5638输出电流_tlv5638 IO控制

TLV5638.rar_MSP430F4260_TLV5638_hcs12 tlv5638

TLV5613.rar_TLV5613_tlv56

tlv5636.rar_tlv5636

TLV1571.rar_54xx_tlv1571

ads7886-tlv5616.rar_TLV5616_ads7886 51 程序_fpga TLV5616_msp430 tl

TLV5638.rar_TLV5638

冰河的渗透实战笔记-冰河.pdf

大灰狼远控2021最新版，解压密码222

J-LINK V10 V11固件.rar

ISO21434.pdf

Web安全漏洞扫描工具-AWVS14

stm32f103 adc采样+dma传输+fft处理 频率计_fft处理_stm32_ADCFFT_频率计_ADC采样_

CTF 竞赛入门指南（ctf-all-in-one）.pdf

Web中间件常见漏洞总结.pdf

jts-1.14.zip

最新资源

stm32f103 adc采样+dma传输+fft处理频率计_fft处理_stm32_ADCFFT_频率计_ADC采样_