library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD1602 is
Port (
CLK : in std_logic;
Reset : in std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic;
LCD_EN : out std_logic;
data : out std_logic_vector(3 downto 0));
end LCD1602;
architecture Behavioral of LCD1602 is
type iState is (
Write_instr, --写命令字
Write_DataUP4_1, --写 LCD 一线高 4 位
Write_DataDown4_1, --写 LCD 一线低 4 位
Set_DDRamAddUp, --设置 DDRam 地址高 4 位
Set_DDRamAddDown, --设置 DDRam 地址低 4 位
Write_DataUP4_2, --写 LCD 二线高 4 位
Write_DataDown4_2 --写 LCD 二线低 4 位
);
signal State:iState;
type Ram is array(0 to 15) of std_logic_vector(7 downto 0);
constant
MyRamUp:Ram:=(x"46",x"68",x"69",x"73",x"20",x"49",x"73",x"20",x"4d",x"79",
x"20",x"46",x"69",x"72",x"73",x"74");
--This Is My First
constant
MyRamDown:Ram:=(x"20",x"20",x"46",x"50",x"47",x"41",x"20",x"50",x"72",x"6
f",x"67",x"72",x"61",x"6d",x"20",x"20");
--FPGA Program
signal LCD_Clk : std_logic :='0';
signal datacnt : integer range 0 to 15:=0;
begin
LCD_RW <= '0';
LCD_EN <= LCD_Clk;
process(CLK) --20000 分频,满足
时序要求
variable n1:integer range 0 to 19999;
