c8051f120串口程序，调试成功
//-----------------------------------------------------------------------------
#include <c8051f120.h> // SFR declarations
#define EXTCLK 22118400 // External oscillator frequency in Hz
#define SYSCLK 49760000 // Output of PLL derived from
// (EXTCLK*9/4)
#define BAUDRATE 115200 // Baud rate of UART in bps
// Note: The minimum standard baud rate
// supported by the UART0_Init routine
// in this file is 19,200 bps when
// SYSCLK = 49.76MHz.
#define uchar unsigned char
#define uint unsigned int
sbit LED = P1^6; // LED=’1’ means ON
sbit SW2 = P3^7; // SW2=’0’ means switch pressed
uchar rebuffer;
uint i=0;
//-----------------------------------------------------------------------------
// Function PROTOTYPES
//-----------------------------------------------------------------------------
void main(void);
void SYSCLK_Init(void);
void PORT_Init(void);
void UART0_Init (void);
void delay(unsigned int m)
{
unsigned int n;
n=0;
while(n < m)
{n++;}
return;
}
//-----------------------------------------------------------------------------
// MAIN Routine
//-----------------------------------------------------------------------------
void main (void)
{
WDTCN = 0xde; // disable watchdog timer
WDTCN = 0xad;
PORT_Init (); // initialize crossbar and GPIO
SYSCLK_Init (); // initialize oscillator
UART0_Init (); // initialize UART0
SFRPAGE = UART0_PAGE; // Direct printf output to UART0
EA=1;
LED=1;
while(1)
{
for(i=0; i<6; i++) /*延时*/
{
delay(60000);
}
}
}
//-----------------------------------------------------------------------------
// Initialization Routines
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// SYSCLK_Init
//-----------------------------------------------------------------------------
//
// This routine initializes the system clock to use an external 22.1184 MHz
// crystal oscillator multiplied by a factor of 9/4 using the PLL as its
// clock source. The resulting frequency is 22.1184 MHz * 9/4 = 49.7664 MHz
//
void SYSCLK_Init (void)
{
int i; // delay counter
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
SFRPAGE = CONFIG_PAGE; // set SFR page
OSCXCN = 0x67; // start external oscillator with
// 22.1184MHz crystal
for (i=0; i < 256; i++) ; // Wait for osc. to start up
while (!(OSCXCN & 0x80)) ; // Wait for crystal osc. to settle
CLKSEL = 0x01; // Select the external osc. as
// the SYSCLK source
OSCICN = 0x00; // Disable the internal osc.
//Turn on the PLL and increase the system clock by a factor of M/N = 9/4
SFRPAGE = CONFIG_PAGE;
PLL0CN = 0x04; // Set PLL source as external osc.
SFRPAGE = LEGACY_PAGE;
FLSCL = 0x10; // Set FLASH read time for 50MHz clk
// or less
SFRPAGE = CONFIG_PAGE;
PLL0CN |= 0x01; // Enable Power to PLL
PLL0DIV = 0x04; // Set Pre-divide value to N (N = 4)
PLL0FLT = 0x01; // Set the PLL filter register for
// a reference clock from 19 - 30 MHz
// and an output clock from 45 - 80 MHz
PLL0MUL = 0x09; // Multiply SYSCLK by M (M = 9)
for (i=0; i < 256; i++) ; // Wait at least 5us
PLL0CN |= 0x02; // Enable the PLL
while(!(PLL0CN & 0x10)); // Wait until PLL frequency is locked
CLKSEL = 0x02; // Select PLL as SYSCLK source
SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
}
//-----------------------------------------------------------------------------
// PORT_Init
//-----------------------------------------------------------------------------
void PORT_Init (void)
{
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
SFRPAGE = CONFIG_PAGE; // set SFR page
XBR0 = 0x04; // Enable UART0
XBR1 = 0x00;
XBR2 = 0x40; // Enable crossbar and weak pull-up
P0MDOUT |= 0x01; // Set TX0 pin to push-pull
P1MDOUT |= 0x40; // Set P1.6(LED) to push-pull
SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
}
//-----------------------------------------------------------------------------
// UART0_Init
//-----------------------------------------------------------------------------
// Configure the UART0 using Timer1, for <baudrate> and 8-N-1. In order to
// increase the clocking flexibility of Timer0, Timer1 is configured to count
// SYSCLKs.
//
// To use this routine SYSCLK/BAUDRATE/16 must be less than 256. For example,
// if SYSCLK = 50 MHz, the lowest standard baud rate supported by this
// routine is 19,200 bps.
//
void UART0_Init (void)
{
char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
SFRPAGE = UART0_PAGE;
SCON0 = 0x50; // SCON0: mode 0, 8-bit UART, enable RX
SSTA0 = 0x10; // Timer 1 generates UART0 baud rate and
// UART0 baud rate divide by two disabled
SFRPAGE = TIMER01_PAGE;
TMOD &= ~0xF0;
TMOD |= 0x20; // TMOD: timer 1, mode 2, 8-bit reload
TH1 = -(SYSCLK/BAUDRATE/16); // Set the Timer1 reload value
// When using a low baud rate, this equation
// should be checked to ensure that the
// reload value will fit in 8-bits.
CKCON |= 0x10; // T1M = 1; SCA1:0 = xx
TL1 = TH1; // initialize Timer1
TR1 = 1; // start Timer1
SFRPAGE = UART0_PAGE;
TI0 = 1; // Indicate TX0 ready
SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
ES0=1;
}
void UART0_ISR (void) interrupt 4
{
if(RI0)
{
LED=~LED;
RI0=0;
rebuffer=SBUF0;
SBUF0=rebuffer;
if(TI0)
{TI0=0;}
}
}
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