DSP280x_examples.rar_280X_280x can _DSP F280x examples_DSP280X的

// TI File $Revision: /main/4 $ // Checkin $Date: September 15, 2005 11:00:48 $ //########################################################################### // // FILE: Example_280xSWPrioritizedDefaultIsr.c // // TITLE: DSP280x Device Default Software Prioritized Interrupt Service Routines. // // This file is based on the standard DSP280x_SWPrioritizedDefaultIsr.c // The ISR routines have been modified slightly to provide a trace // mechanism used for this example // //########################################################################### // // $TI Release: DSP280x, DSP2801x Header Files V1.41 $ // $Release Date: August 7th, 2006 $ //########################################################################### #include "DSP280x_Device.h" // DSP280x Headerfile Include File #include "DSP280x_Examples.h" // DSP280x Examples Include File #include "DSP280x_SWPrioritizedIsrLevels.h" // Defined in the Example_28xSWPrioritizedInterrupts.c file // for this example only extern Uint16 ISRTrace[50]; extern Uint16 ISRTraceIndex; // Used for ISR delays Uint16 i; // Connected to INT13 of CPU (use MINT13 mask): // Note CPU-Timer1 is reserved for TI use, however XINT13 // ISR can be used by the user. #if (INT13PL != 0) interrupt void INT13_ISR(void) // INT13 or CPU-Timer1 { IER |= MINT13; // Set "global" priority EINT; // Insert ISR Code here // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } #endif // Connected to INT14 of CPU (use MINT14 mask): #if (INT14PL != 0) interrupt void INT14_ISR(void) // CPU-Timer2 { IER |= MINT14; // Set "global" priority EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } #endif // Connected to INT15 of CPU (use MINT15 mask): #if (INT15PL != 0) interrupt void DATALOG_ISR(void) // Datalogging interrupt { IER |= MINT15; // Set "global" priority EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } #endif // Connected to INT16 of CPU (use MINT16 mask): #if (INT16PL != 0) interrupt void RTOSINT_ISR(void) // RTOS interrupt { IER |= MINT16; // Set "global" priority EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } #endif // Connected to EMUINT of CPU (non-maskable): interrupt void EMUINT_ISR(void) // Emulation interrupt { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to NMI of CPU (non-maskable): interrupt void NMI_ISR(void) // Non-maskable interrupt { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to ITRAP of CPU (non-maskable): interrupt void ILLEGAL_ISR(void) // Illegal operation TRAP { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER1 of CPU (non-maskable): interrupt void USER1_ISR(void) // User Defined trap 1 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER2 of CPU (non-maskable): interrupt void USER2_ISR(void) // User Defined trap 2 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER3 of CPU (non-maskable): interrupt void USER3_ISR(void) // User Defined trap 3 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER4 of CPU (non-maskable): interrupt void USER4_ISR(void) // User Defined trap 4 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER5 of CPU (non-maskable): interrupt void USER5_ISR(void) // User Defined trap 5 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER6 of CPU (non-maskable): interrupt void USER6_ISR(void) // User Defined trap 6 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER7 of CPU (non-maskable): interrupt void USER7_ISR(void) // User Defined trap 7 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER8 of CPU (non-maskable): interrupt void USER8_ISR(void) // User Defined trap 8 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER9 of CPU (non-maskable): interrupt void USER9_ISR(void) // User Defined trap 9 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER10 of CPU (non-maskable): interrupt void USER10_ISR(void) // User Defined trap 10 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER11 of CPU (non-maskable): interrupt void USER11_ISR(void) // User Defined trap 11 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // Connected to USER12 of CPU (non-maskable): interrupt void USER12_ISR(void) // User Defined trap 12 { EINT; // Insert ISR Code here....... // Next two lines for debug only to halt the processor here // Remove after inserting ISR Code asm (" ESTOP0"); for(;;); } // ----------------------------------------------------------- // PIE Group 1 - MUXed into CPU INT1 // ----------------------------------------------------------- // Connected to PIEIER1_1 (use MINT1 and MG11 masks): #if (G11PL != 0) interrupt void SEQ1INT_ISR( void ) // ADC { // Set interrupt priority: volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all; IER |= M_INT1; IER &= MINT1; // Set "global" priority PieCtrlRegs.PIEIER1.all &= MG11; // Set "group" priority PieCtrlRegs.PIEACK.all = 0xFFFF; // E