2
AVR136
8020A-AVR-05/06
2 Principles
The software example presented here demonstrates the generation of ten PWM
channels on an ATtiny2313, but is equally applicable to any other AVR with an 8-bit
timer capable of generating an overflow interrupt. Low jitter is achieved by having the
timer overflow as the only enabled interrupt, and by having the output signals updated
during the first instructions in the interrupt service routine (ISR). This makes the
execution tempo very predictable, the only jitter being variations in interrupt response
time which depends on the instruction being executed at the exact moment the
interrupt occurs, giving a typical jitter of +/-1 clock cycle. With the full PWM cycle time
being 65536 clock cycles, jitter is therefore +/-0.0015% of the PWM base frequency
and is non-cumulative over time.
The general principle of the software PWM is to mimic the operation of the hardware
timers in PWM mode. An array of ‘compare’ values is established with elements set to
the required PWM pulse widths, and a complementary ‘compbuff’ array is used to
double-buffer any compare array update, ensuring consistent PWM operation. An 8-
bit timer is initialized to count the main clock and generate an interrupt on overflow, so
an interrupt occurs once every 256-clock cycles. This means the ISR must complete
in less than 256 cycles to maintain the low jitter specification. An 8-bit soft counter is
incremented during each ISR to act as a position indicator within the PWM cycle,
giving a PWM resolution of 1/256 or ~0.4%, and an overall PWM base frequency of
main clock / (256 * 256).
3 Interrupt Service Routine
A logical approach for the ISR would be to increment the soft counter, determine
which PWM signals should change state at that position of the PWM cycle, then
implement the changes. The problem with this is that the time taken between the start
of the ISR and the pin state change will vary considerably depending on the results of
the PWM position tests, causing significant jitter. To eliminate this the ISR performs
the pin state update immediately, then carries out the increment and position tests to
prepare the state values for the start of the next interrupt cycle. On overflow of the
soft counter all pin conditions are prepared for being set high and the compare values
are updated with any changes made to the compbuff values. If a compare value is
zero the pin condition indicator will be returned to zero, so a PWM value of zero will
give an output that is permanently low. The maximum PWM pulse width will be
255/256 of the base frequency period.
4 DEBUG Option
In order to maintain the specified jitter performance, the ISR must complete within
256 clock cycles. The worst-case situation occurs in the softcount=0 ISR when all but
one channels have a compare value of zero, so the DEBUG option has been included
to allow checking of the ISR timing when channel quantity has been modified. (Note:
all channels being zero is theoretically worse, but as no channel is producing a PWM
pulse any timing overflow will not be seen). Changing the DEBUG define to 1 allows
the approximate time taken by the ISR to be measured by Timer 1, with the default
channel settings changed to give the worst-case conditions, and the Timer 1 result is
frequently displayed on an attached RS232 terminal. Ideally the ISR time displayed
should be well below 0x00FF. A debug pin is also enabled allowing an oscilloscope to
be used to view the ISR timing, with a typical waveform shown in
Figure 4-1.
