rockchip_i2s.rar_SOC_linux i2s_linux i2s driver

/* sound/soc/rockchip/rockchip_i2s.c * * ALSA SoC Audio Layer - Rockchip I2S Controller driver * * Copyright (c) 2014 Rockchip Electronics Co. Ltd. * Author: Jianqun <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include <linux/module.h> #include <linux/delay.h> #include <linux/of_gpio.h> #include <linux/clk.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <sound/pcm_params.h> #include <sound/dmaengine_pcm.h> #include "rockchip_i2s.h" #define DRV_NAME "rockchip-i2s" struct rk_i2s_dev { struct device *dev; struct clk *hclk; struct clk *mclk; struct snd_dmaengine_dai_dma_data capture_dma_data; struct snd_dmaengine_dai_dma_data playback_dma_data; struct regmap *regmap; /* * Used to indicate the tx/rx status. * I2S controller hopes to start the tx and rx together, * also to stop them when they are both try to stop. */ bool tx_start; bool rx_start; }; static int i2s_runtime_suspend(struct device *dev) { struct rk_i2s_dev *i2s = dev_get_drvdata(dev); clk_disable_unprepare(i2s->mclk); return 0; } static int i2s_runtime_resume(struct device *dev) { struct rk_i2s_dev *i2s = dev_get_drvdata(dev); int ret; ret = clk_prepare_enable(i2s->mclk); if (ret) { dev_err(i2s->dev, "clock enable failed %d\n", ret); return ret; } return 0; } static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) { return snd_soc_dai_get_drvdata(dai); } static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) { unsigned int val = 0; int retry = 10; if (on) { regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START, I2S_XFER_TXS_START | I2S_XFER_RXS_START); i2s->tx_start = true; } else { i2s->tx_start = false; regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); if (!i2s->rx_start) { regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START, I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); regmap_update_bits(i2s->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC | I2S_CLR_RXC); regmap_read(i2s->regmap, I2S_CLR, &val); /* Should wait for clear operation to finish */ while (val) { regmap_read(i2s->regmap, I2S_CLR, &val); retry--; if (!retry) { dev_warn(i2s->dev, "fail to clear\n"); break; } } } } } static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) { unsigned int val = 0; int retry = 10; if (on) { regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START, I2S_XFER_TXS_START | I2S_XFER_RXS_START); i2s->rx_start = true; } else { i2s->rx_start = false; regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); if (!i2s->tx_start) { regmap_update_bits(i2s->regmap, I2S_XFER, I2S_XFER_TXS_START | I2S_XFER_RXS_START, I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP); regmap_update_bits(i2s->regmap, I2S_CLR, I2S_CLR_TXC | I2S_CLR_RXC, I2S_CLR_TXC | I2S_CLR_RXC); regmap_read(i2s->regmap, I2S_CLR, &val); /* Should wait for clear operation to finish */ while (val) { regmap_read(i2s->regmap, I2S_CLR, &val); retry--; if (!retry) { dev_warn(i2s->dev, "fail to clear\n"); break; } } } } } static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) { struct rk_i2s_dev *i2s = to_info(cpu_dai); unsigned int mask = 0, val = 0; mask = I2S_CKR_MSS_MASK; switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* Set source clock in Master mode */ val = I2S_CKR_MSS_MASTER; break; case SND_SOC_DAIFMT_CBM_CFM: val = I2S_CKR_MSS_SLAVE; break; default: return -EINVAL; } regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); mask = I2S_TXCR_IBM_MASK; switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_RIGHT_J: val = I2S_TXCR_IBM_RSJM; break; case SND_SOC_DAIFMT_LEFT_J: val = I2S_TXCR_IBM_LSJM; break; case SND_SOC_DAIFMT_I2S: val = I2S_TXCR_IBM_NORMAL; break; default: return -EINVAL; } regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); mask = I2S_RXCR_IBM_MASK; switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_RIGHT_J: val = I2S_RXCR_IBM_RSJM; break; case SND_SOC_DAIFMT_LEFT_J: val = I2S_RXCR_IBM_LSJM; break; case SND_SOC_DAIFMT_I2S: val = I2S_RXCR_IBM_NORMAL; break; default: return -EINVAL; } regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); return 0; } static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct rk_i2s_dev *i2s = to_info(dai); unsigned int val = 0; switch (params_format(params)) { case SNDRV_PCM_FORMAT_S8: val |= I2S_TXCR_VDW(8); break; case SNDRV_PCM_FORMAT_S16_LE: val |= I2S_TXCR_VDW(16); break; case SNDRV_PCM_FORMAT_S20_3LE: val |= I2S_TXCR_VDW(20); break; case SNDRV_PCM_FORMAT_S24_LE: val |= I2S_TXCR_VDW(24); break; default: return -EINVAL; } regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val); regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val); return 0; } static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { struct rk_i2s_dev *i2s = to_info(dai); int ret = 0; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) rockchip_snd_rxctrl(i2s, 1); else rockchip_snd_txctrl(i2s, 1); break; case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) rockchip_snd_rxctrl(i2s, 0); else rockchip_snd_txctrl(i2s, 0); break; default: ret = -EINVAL; break; } return ret; } static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, unsigned int freq, int dir) { struct rk_i2s_dev *i2s = to_info(cpu_dai); int ret; ret = clk_set_rate(i2s->mclk, freq); if (ret) dev_err(i2s->dev, "Fail to set mclk %d\n", ret); return ret; } static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) { struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); dai->capture_dma_data = &i2s->capture_dma_data; dai->playback_dma_data = &i2s->playback_dma_data; return 0; } static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { .hw_params = rockchip_i2s_hw_params, .set_sysclk = rockchip_i2s_set_sysclk, .set_fmt = rockchip_i2s_set_fmt, .trigger = rockchip_i2s_trigger, }; static struct snd_soc_dai_driver rockchip_i2s_dai = { .probe = rockchip_i2s_dai_probe, .playback = { .stream_name = "Playback", .channels_min = 2, .channels_max = 8, .rates = SNDRV_PCM_RATE_8000_192000, .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE), }, .capture = { .stream_name = "Capture", .channels_min = 2, .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_192000, .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE), }, .ops = &rockchip_i2s_dai_ops, }; static const struct snd_soc_component_driver rockchip_i2s_component = { .name = DRV_NAME, }; static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) { switch (reg) { case I2S_TXCR: case I2S_RXCR: case I2S_CKR: case I2S_DMACR: case I2S_INTCR: