mxc_nand.rar_operation

#include <linux/delay.h> #include <linux/slab.h> #include <linux/init.h> #include <linux/module.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/interrupt.h> #include <linux/device.h> #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/completion.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/of_mtd.h> #include <asm/mach/flash.h> #include <linux/platform_data/mtd-mxc_nand.h> #define DRIVER_NAME "mxc_nand" /* Addresses for NFC registers */ #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06) #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08) #define NFC_V1_V2_CONFIG (host->regs + 0x0a) #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c) #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e) #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10) #define NFC_V1_V2_WRPROT (host->regs + 0x12) #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14) #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16) #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20) #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24) #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28) #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c) #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22) #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26) #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a) #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e) #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18) #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a) #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c) #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) #define NFC_V1_V2_CONFIG1_BIG (1 << 5) #define NFC_V1_V2_CONFIG1_RST (1 << 6) #define NFC_V1_V2_CONFIG1_CE (1 << 7) #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) #define NFC_V2_CONFIG1_FP_INT (1 << 11) #define NFC_V1_V2_CONFIG2_INT (1 << 15) /* * Operation modes for the NFC. Valid for v1, v2 and v3 * type controllers. */ #define NFC_CMD (1 << 0) #define NFC_ADDR (1 << 1) #define NFC_INPUT (1 << 2) #define NFC_OUTPUT (1 << 3) #define NFC_ID (1 << 4) #define NFC_STATUS (1 << 5) #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) #define NFC_V3_CONFIG1 (host->regs_axi + 0x34) #define NFC_V3_CONFIG1_SP_EN (1 << 0) #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) #define NFC_V3_LAUNCH (host->regs_axi + 0x40) #define NFC_V3_WRPROT (host->regs_ip + 0x0) #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) #define NFC_V3_WRPROT_LOCK (1 << 1) #define NFC_V3_WRPROT_UNLOCK (1 << 2) #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) #define NFC_V3_CONFIG2 (host->regs_ip + 0x24) #define NFC_V3_CONFIG2_PS_512 (0 << 0) #define NFC_V3_CONFIG2_PS_2048 (1 << 0) #define NFC_V3_CONFIG2_PS_4096 (2 << 0) #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) #define NFC_V3_CONFIG2_ECC_EN (1 << 3) #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift) #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) #define NFC_V3_CONFIG2_INT_MSK (1 << 15) #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) #define NFC_V3_CONFIG3 (host->regs_ip + 0x28) #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) #define NFC_V3_CONFIG3_FW8 (1 << 3) #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) #define NFC_V3_CONFIG3_RBB_MODE (1 << 15) #define NFC_V3_CONFIG3_NO_SDMA (1 << 20) #define NFC_V3_IPC (host->regs_ip + 0x2C) #define NFC_V3_IPC_CREQ (1 << 0) #define NFC_V3_IPC_INT (1 << 31) #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) struct mxc_nand_host; struct mxc_nand_devtype_data { void (*preset)(struct mtd_info *); void (*send_cmd)(struct mxc_nand_host *, uint16_t, int); void (*send_addr)(struct mxc_nand_host *, uint16_t, int); void (*send_page)(struct mtd_info *, unsigned int); void (*send_read_id)(struct mxc_nand_host *); uint16_t (*get_dev_status)(struct mxc_nand_host *); int (*check_int)(struct mxc_nand_host *); void (*irq_control)(struct mxc_nand_host *, int); u32 (*get_ecc_status)(struct mxc_nand_host *); struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k; void (*select_chip)(struct mtd_info *mtd, int chip); int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); /* * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked * (CONFIG1:INT_MSK is set). To handle this the driver uses * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK */ int irqpending_quirk; int needs_ip; size_t regs_offset; size_t spare0_offset; size_t axi_offset; int spare_len; int eccbytes; int eccsize; int ppb_shift; }; struct mxc_nand_host { struct mtd_info mtd; struct nand_chip nand; struct device *dev; void __iomem *spare0; void __iomem *main_area0; void __iomem *base; void __iomem *regs; void __iomem *regs_axi; void __iomem *regs_ip; int status_request; struct clk *clk; int clk_act; int irq; int eccsize; int active_cs; struct completion op_completion; uint8_t *data_buf; unsigned int buf_start; const struct mxc_nand_devtype_data *devtype_data; struct mxc_nand_platform_data pdata; }; /* OOB placement block for use with hardware ecc generation */ static struct nand_ecclayout nandv1_hw_eccoob_smallpage = { .eccbytes = 5, .eccpos = {6, 7, 8, 9, 10}, .oobfree = {{0, 5}, {12, 4}, } }; static struct nand_ecclayout nandv1_hw_eccoob_largepage = { .eccbytes = 20, .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26, 38, 39, 40, 41, 42, 54, 55, 56, 57, 58}, .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, } }; /* OOB description for 512 byte pages with 16 byte OOB */ static struct nand_ecclayout nandv2_hw_eccoob_smallpage = { .eccbytes = 1 * 9, .eccpos = { 7, 8, 9, 10, 11, 12, 13, 14, 15 }, .oobfree = { {.offset = 0, .length = 5} } }; /* OOB description for 2048 byte pages with 64 byte OOB */ static struct nand_ecclayout nandv2_hw_eccoob_largepage = { .eccbytes = 4 * 9, .eccpos = { 7, 8, 9, 10, 11, 12, 13, 14, 15, 23, 24, 25, 26, 27, 28, 29, 30, 31, 39, 40, 41, 42, 43, 44, 45, 46, 47, 55, 56, 57, 58, 59, 60, 61, 62, 63 }, .oobfree = { {.offset = 2, .length = 4}, {.offset = 16, .length = 7}, {.offset = 32, .length = 7}, {.offset = 48, .length = 7} } }; /* OOB description for 4096 byte pages with 128 byte OOB */ static struct nand_ecclayout nandv2_hw_eccoob_4k = { .eccbytes = 8 * 9, .eccpos = { 7, 8, 9, 10, 11, 12, 13, 14, 15, 23, 24, 25, 26, 27, 28, 29, 30, 31, 39, 40, 41, 42, 43, 44, 45, 46, 47, 55, 56, 57, 58, 59, 60, 61, 62, 63, 71, 72, 73, 74, 75, 76, 77, 78, 79, 87, 88, 89, 90, 91, 92, 93, 94, 95, 103, 104, 105, 106, 107, 108, 109, 110, 111, 119, 120, 121, 122, 123, 124, 125, 126, 127, }, .oobfree = { {.offset = 2, .length = 4}, {.offset = 16, .length = 7}, {.offset = 32, .length = 7}, {.offset = 48, .length = 7}, {.offset = 64, .length = 7}, {.offset = 80, .length = 7}, {.offset = 96, .length = 7}, {.offset = 112, .length = 7}, } }; static const char * const part_probes[] = { "cmdlinepart", "RedBoot", "ofpart", NULL }; static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) { int i; u32 *t = trg; const __iomem u32 *s = src