CHAPTER
10
EXTERNAL SRAM
10.1
INTRODUCTION
Random access memory
(RAM)
is used for massive storage in a digital system since a
RAM
cell is much simpler than an
FF
cell.
A
commonly used type
of
RAM
is the asynchronous
static
RAM (SRAM).
Unlike a register, in which the data is sampled and stored at an edge
of a clock signal, accessing data from an asynchronous
SRAM
is more complicated.
A
read or write operation requires that the data, address, and control signals be asserted
in
a specific order, and these signals must be stable for a certain amount of time during the
operation.
It is difficult for a synchronous system to access an
SRAM
directly. We usually use
a
memory
controller
as the interface, which takes commands from the main system syn-
chronously and then generates properly timed signals to access the
SRAM.
The controller
shields the main system from the detailed timing and makes the memory access appears
like a synchronous operation. The performance of a memory controller is measured by the
number
of
memory accesses that can be completed in a given period. While designing a
simple memory controller is straightforward, achieving optimal performance involves many
timing issues and is quite difficult.
The
S3
board has two 256K-by-16 asynchronous
SRAM
devices, which total
1M
bytes.
In this chapter, we demonstrate the construction of a memory controller for these devices.
Since the timing characteristics of each
RAM
device
are
different, the controller is applicable
only to this particular device. However, the same design principle can be used for similar
FPGA
Prototjping
bj.
VHDL
Examples.
By
Pang
F?
Chu
Copyright
@
2008
John
Wiley
&
Sons,
Inc.
21
5
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