rbtree_augmented.rar_EVEREST

/* bnx2x_stats.c: Broadcom Everest network driver. * * Copyright (c) 2007-2013 Broadcom Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation. * * Maintained by: Ariel Elior <ariel.elior@qlogic.com> * Written by: Eliezer Tamir * Based on code from Michael Chan's bnx2 driver * UDP CSUM errata workaround by Arik Gendelman * Slowpath and fastpath rework by Vladislav Zolotarov * Statistics and Link management by Yitchak Gertner * */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include "bnx2x_stats.h" #include "bnx2x_cmn.h" #include "bnx2x_sriov.h" /* Statistics */ /* * General service functions */ static inline long bnx2x_hilo(u32 *hiref) { u32 lo = *(hiref + 1); #if (BITS_PER_LONG == 64) u32 hi = *hiref; return HILO_U64(hi, lo); #else return lo; #endif } static inline u16 bnx2x_get_port_stats_dma_len(struct bnx2x *bp) { u16 res = 0; /* 'newest' convention - shmem2 cotains the size of the port stats */ if (SHMEM2_HAS(bp, sizeof_port_stats)) { u32 size = SHMEM2_RD(bp, sizeof_port_stats); if (size) res = size; /* prevent newer BC from causing buffer overflow */ if (res > sizeof(struct host_port_stats)) res = sizeof(struct host_port_stats); } /* Older convention - all BCs support the port stats' fields up until * the 'not_used' field */ if (!res) { res = offsetof(struct host_port_stats, not_used) + 4; /* if PFC stats are supported by the MFW, DMA them as well */ if (bp->flags & BC_SUPPORTS_PFC_STATS) { res += offsetof(struct host_port_stats, pfc_frames_rx_lo) - offsetof(struct host_port_stats, pfc_frames_tx_hi) + 4 ; } } res >>= 2; WARN_ON(res > 2 * DMAE_LEN32_RD_MAX); return res; } /* * Init service functions */ static void bnx2x_dp_stats(struct bnx2x *bp) { int i; DP(BNX2X_MSG_STATS, "dumping stats:\n" "fw_stats_req\n" " hdr\n" " cmd_num %d\n" " reserved0 %d\n" " drv_stats_counter %d\n" " reserved1 %d\n" " stats_counters_addrs %x %x\n", bp->fw_stats_req->hdr.cmd_num, bp->fw_stats_req->hdr.reserved0, bp->fw_stats_req->hdr.drv_stats_counter, bp->fw_stats_req->hdr.reserved1, bp->fw_stats_req->hdr.stats_counters_addrs.hi, bp->fw_stats_req->hdr.stats_counters_addrs.lo); for (i = 0; i < bp->fw_stats_req->hdr.cmd_num; i++) { DP(BNX2X_MSG_STATS, "query[%d]\n" " kind %d\n" " index %d\n" " funcID %d\n" " reserved %d\n" " address %x %x\n", i, bp->fw_stats_req->query[i].kind, bp->fw_stats_req->query[i].index, bp->fw_stats_req->query[i].funcID, bp->fw_stats_req->query[i].reserved, bp->fw_stats_req->query[i].address.hi, bp->fw_stats_req->query[i].address.lo); } } /* Post the next statistics ramrod. Protect it with the spin in * order to ensure the strict order between statistics ramrods * (each ramrod has a sequence number passed in a * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be * sent in order). */ static void bnx2x_storm_stats_post(struct bnx2x *bp) { if (!bp->stats_pending) { int rc; spin_lock_bh(&bp->stats_lock); if (bp->stats_pending) { spin_unlock_bh(&bp->stats_lock); return; } bp->fw_stats_req->hdr.drv_stats_counter = cpu_to_le16(bp->stats_counter++); DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n", le16_to_cpu(bp->fw_stats_req->hdr.drv_stats_counter)); /* adjust the ramrod to include VF queues statistics */ bnx2x_iov_adjust_stats_req(bp); bnx2x_dp_stats(bp); /* send FW stats ramrod */ rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0, U64_HI(bp->fw_stats_req_mapping), U64_LO(bp->fw_stats_req_mapping), NONE_CONNECTION_TYPE); if (rc == 0) bp->stats_pending = 1; spin_unlock_bh(&bp->stats_lock); } } static void bnx2x_hw_stats_post(struct bnx2x *bp) { struct dmae_command *dmae = &bp->stats_dmae; u32 *stats_comp = bnx2x_sp(bp, stats_comp); *stats_comp = DMAE_COMP_VAL; if (CHIP_REV_IS_SLOW(bp)) return; /* Update MCP's statistics if possible */ if (bp->func_stx) memcpy(bnx2x_sp(bp, func_stats), &bp->func_stats, sizeof(bp->func_stats)); /* loader */ if (bp->executer_idx) { int loader_idx = PMF_DMAE_C(bp); u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, true, DMAE_COMP_GRC); opcode = bnx2x_dmae_opcode_clr_src_reset(opcode); memset(dmae, 0, sizeof(struct dmae_command)); dmae->opcode = opcode; dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0])); dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0])); dmae->dst_addr_lo = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * (loader_idx + 1)) >> 2; dmae->dst_addr_hi = 0; dmae->len = sizeof(struct dmae_command) >> 2; if (CHIP_IS_E1(bp)) dmae->len--; dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2; dmae->comp_addr_hi = 0; dmae->comp_val = 1; *stats_comp = 0; bnx2x_post_dmae(bp, dmae, loader_idx); } else if (bp->func_stx) { *stats_comp = 0; bnx2x_issue_dmae_with_comp(bp, dmae, stats_comp); } } static void bnx2x_stats_comp(struct bnx2x *bp) { u32 *stats_comp = bnx2x_sp(bp, stats_comp); int cnt = 10; might_sleep(); while (*stats_comp != DMAE_COMP_VAL) { if (!cnt) { BNX2X_ERR("timeout waiting for stats finished\n"); break; } cnt--; usleep_range(1000, 2000); } } /* * Statistics service functions */ /* should be called under stats_sema */ static void __bnx2x_stats_pmf_update(struct bnx2x *bp) { struct dmae_command *dmae; u32 opcode; int loader_idx = PMF_DMAE_C(bp); u32 *stats_comp = bnx2x_sp(bp, stats_comp); /* sanity */ if (!bp->port.pmf || !bp->port.port_stx) { BNX2X_ERR("BUG!\n"); return; } bp->executer_idx = 0; opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0); dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC); dmae->src_addr_lo = bp->port.port_stx >> 2; dmae->src_addr_hi = 0; dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats)); dmae->len = DMAE_LEN32_RD_MAX; dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2; dmae->comp_addr_hi = 0; dmae->comp_val = 1; dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI); dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX; dmae->src_addr_hi = 0; dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) + DMAE_LEN32_RD_MAX * 4); dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) + DMAE_LEN32_RD_MAX * 4); dmae->len = bnx2x_get_port_stats_dma_len(bp) - DMAE_LEN32_RD_MAX; dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp)); dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp)); dmae->comp_val = DMAE_COMP_VAL; *stats_comp = 0; bnx2x_hw_stats_post(bp); bnx2x_stats_comp(bp); } static void bnx2x_port_stats_init(struct bnx2x *bp) { struct dmae_command *dmae; int port = BP_PORT(bp); u32 opcode; int loader_idx = PMF_DMAE_C(bp); u32 mac_addr; u32 *stats_comp = bnx2x_sp(bp, stats_comp); /* sanity */ if (!bp->link_vars.link_up || !bp->port.pmf) { BNX2X_ERR("BUG!\n"); return; } bp->executer_idx = 0; /* MCP */ opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, true, DMAE_COMP_GRC); if (bp->port.port_stx) { dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); dmae->opcode = opcode; dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats)); dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats)); dmae->dst_addr_lo = bp->port.port_stx >> 2; dmae->dst_addr_hi = 0; dmae->len = bnx2x_get_port_stats_dma_len(bp); dmae->comp_addr_lo = dmae_reg_go_c[loader_idx]