I2C.zip_i2c

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rd1006_01

I

July 2001 Reference Design RD1006

Introduction

The I

C bus provides a simple two-wire means of communication. This protocol is used in many applications.

intended to be a simple controller providing random reads cycles only. Typically, serial EEPROMs are programmed

at board assembly time and store configuration information, which is read by a microprocessor during power-up.

This design was implemented in Verilog, synthesized and fitted using Lattice’s ispDesignEXPERT™ software into a

ispMACH™ 4A device. The design requires 46 macrocells and 24 I/O pins. Using an M4A-64/32-55 yields greater

than 153MHz performance. Results may vary according to the synthesis tool.

This design assumes the user has experience with I

Applicable Documents section, below, is not repeated in this document.

Applicable Documents

• National NM24C16 16,384-Bit Serial EEPROM

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supports random read cycles only. The design consists of the following modules:

• I2c_sep Top level module

• I2c_clk Clock generation module

• I2c_rreg Read register module

• I2c_st State machine module

• I2c_tbuf Tri-state buffer module

•I2c_wreg Write register module

Top Level Signal Description

Table 1 provides the input/output signals of the I

C Controller. Signals ending with “_L” indicate an active low signal.

Lattice Semiconductor I

C Controller for Serial EEPROMs

2

Table 1. I

2

C Signals

Table 2. I

2

C Registers

Design Module Description

I2C_CLK Module

from the I

2

C device and status information can be read back. The status register bits are defined in Table 3.

Table 3. Status Register Bits

I2C_ST Module

The I2C_state module provides:

• A state machine to control the I

2

• A bit counter to count the bit phases

•I

RD_WR_L Input Write pulse from processor

ADDR[1:0] Input Address bus from microprocessor

DATA[7:0] I/O Microprocessor data bus

CLK Input Input clock

RST_L Input Asynchronous Reset

REG_CLK_IN Input Clock used to latch Word Address

ACK_L Output Microprocessor Cycle Acknowledge

REG_CLK_OUT Output Generated clock to latch Word Address

SCL_PIN Output I

Data 01 Read

Status 10 Read

Bit Signal Description

C cycle is in progress.

Lattice Semiconductor I

C Controller for Serial EEPROMs

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generated. This causes the state machine to start a random read cycle to the address stored in this register.

A clock, reg_clk_out, is generated in this module to allow the use of input registers for the word address register. In

order to use the input registers, this clock signal must be routed on the board to a dedicated clock input pin on the

ispMACH device.

A microprocessor acknowledge signal is provided in this module. This is the chip select signal delayed by one clock

tick. This signal could be omitted from the design if this function is not needed or performed elsewhere.

Test Bench Description

The test bench for this design includes the following modules:

• CLK_RST

• I2C_SLAVE

reset.

I2C_SLAVE Module

The I2C_SLAVE module provides a model of a I

2

C memory device which features 256 memory locations. The slave

module is able to detect START and STOP commands from the I

2

C controller. It generates ACK after the word

address cycle and leaves the I

2

C bus tristated after data read. The data stored in the memory is the same as its

Data Transmitted on Read” messages during simulation.

2

2

C

Controller.

Design Flow

Simulation

level simulation.