7/28/2010 1 Version 0.04
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
ÁЉꗬꗬ
NT35510
One-chip Driver IC with internal GRAM
for 16.7M colors 480RGB x 864 a-Si TFT LCD
with CPU / RGB / MIPI / MDDI Interface
or without internal CGRAM
for 16.7M colors 480RGB x 1024 a-Si TFT LCD
with RGB Interface
V0.04
Preliminary
PRELIMINARY NT35510
7/28/2010 2 Version 0.04
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
REVISION HISTORY................................................................................................................................................8
1 DESCRIPTION ....................................................................................................................................................11
1.1
PURPOSE OF THIS DOCUMENT .............................................................................................................................11
1.2
GENERAL DESCRIPTION ......................................................................................................................................11
2 FEATURES .........................................................................................................................................................12
3 BLOCK DIAGRAM..............................................................................................................................................14
4 PIN DESCRIPTION .............................................................................................................................................15
4.1
POWER SUPPLY PINS..........................................................................................................................................15
4.2 80-SYSTEM INTERFACE PINS...............................................................................................................................16
4.3
SPI /I2C INTERFACE PINS ...................................................................................................................................16
4.4 RGB INTERFACE PINS ........................................................................................................................................17
4.5
MIPI/MDDI INTERFACE PINS...............................................................................................................................18
4.6 INTERFACE LOGIC PINS.......................................................................................................................................19
4.7
DRIVER OUTPUT PINS .........................................................................................................................................21
4.8 DC/DC CONVERTER PINS ...................................................................................................................................22
4.9 LABC AND CABC CONTROL PINS ...............................................................................................................24
4.10 TEST PINS .....................................................................................................................................................25
5 FUNCTIONAL DESCRIPTION............................................................................................................................26
5.1
MPU INTERFACE.................................................................................................................................................26
5.1.1 Interface Type Selection .......................................................................................................................................26
5.1.2 80-series MPU Interface........................................................................................................................................27
5.1.3 Serial Interface.......................................................................................................................................................45
5.2 I2C INTERFACE...................................................................................................................................................59
5.2.1 Slave Address of I2C.............................................................................................................................................60
5.2.2 Register Write Sequence of I2C Interface ...........................................................................................................60
5.2.3 RAM Data Write Sequence of I2C Interface.........................................................................................................60
5.2.4 Register Read Sequence of I2C Interface ...........................................................................................................64
5.2.5 RAM Data Read Sequence of I2C Interface.........................................................................................................64
5.3 MIPI INTERFACE .................................................................................................................................................68
5.3.1 Display Module Pin Configuration for DSI ..........................................................................................................69
5.3.2 Display Serial Interface (DSI) ...............................................................................................................................70
5.3.3 Memory Write/Read Format................................................................................................................................156
5.3.4 System Power-Up and Initialization...................................................................................................................163
5.4
MDDI INTERFACE .............................................................................................................................................164
5.4.1 MDDI Link Protocol by The NT35510.................................................................................................................165
PRELIMINARY NT35510
7/28/2010 3 Version 0.04
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
5.4.2 MDDI Link Packet Descriptions by the NT35510 ..............................................................................................166
5.4.3 Writing Video Data to Memory Sequence..........................................................................................................176
5.4.4 Writing Register Sequence.................................................................................................................................176
5.4.5 Reading Video Data from Memory Sequence ...................................................................................................177
5.4.6 Reading Register Sequence...............................................................................................................................177
5.4.7 Hibernation Setting.............................................................................................................................................178
5.4.8 MDDI Deep Standby Mode Setting.....................................................................................................................179
5.5 INTERFACE PAUSE ............................................................................................................................................181
5.6 DATA TRANSFER BREAK AND RECOVERY ..........................................................................................................182
5.7
DISPLAY MODULE DATA TRANSFER MODES.......................................................................................................184
5.8 RGB INTERFACE...............................................................................................................................................185
5.8.1 General Description ............................................................................................................................................185
5.8.2 RGB Interface Timing Chart ...............................................................................................................................186
5.8.3 RGB Interface Mode Set .....................................................................................................................................187
5.8.4 RGB Interface Bus Width Set.............................................................................................................................191
5.9 FRAME MEMORY...............................................................................................................................................195
5.9.1 Configuration.......................................................................................................................................................195
5.9.2 Address Counter .................................................................................................................................................196
5.9.3 Interface to Memory Write Direction..................................................................................................................197
5.9.4 Frame Memory to Display Address Mapping....................................................................................................198
5.10 TEARING EFFECT INFORMATION.......................................................................................................................199
5.10.1 Tearing Effect Output Line ...............................................................................................................................199
5.10.2 Tearing Effect Bus Trigger................................................................................................................................204
5.11
CHECKSUM.....................................................................................................................................................216
5.12
POWER ON/OFF SEQUENCE ............................................................................................................................218
5.12.1 Case 1 – RESX line is held High or Unstable by Host at Power On..............................................................219
5.12.2 Case 2 – RESX line is held Low by host at Power On....................................................................................220
5.12.3 Uncontrolled Power Off ....................................................................................................................................220
5.13 POWER LEVEL MODES ....................................................................................................................................221
5.13.1 Definition............................................................................................................................................................221
5.13.2 Power Level Mode Flow Chart..........................................................................................................................222
5.14
RESET FUNCTION ............................................................................................................................................224
5.14.1 Register Default Value ......................................................................................................................................224
5.14.2 Output or Bi-directional (I/O) Pins ...................................................................................................................226
5.14.3 Input Pins...........................................................................................................................................................226
PRELIMINARY NT35510
7/28/2010 4 Version 0.04
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
5.15 SLEEP OUT-COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE ......................................227
5.15.1 Register loading Detection...............................................................................................................................227
5.15.2 Functionality Detection.....................................................................................................................................228
5.15.3 Chip Attachment Detection ..............................................................................................................................229
5.16
DISPLAY PANEL COLOR CHARACTERISTICS.....................................................................................................230
5.17
GAMMA FUNCTION ..........................................................................................................................................231
5.18 BASIC DISPLAY MODE.....................................................................................................................................232
5.19
INSTRUCTION SETTING SEQUENCE...................................................................................................................233
5.19.1 Sleep In/Out Sequence .....................................................................................................................................233
5.19.2 Deep Standby Mode Enter/Exit Sequence.......................................................................................................234
5.20
INSTRUCTION SETUP FLOW .............................................................................................................................235
5.20.1 Initializing with the Built-in Power Supply Circuits........................................................................................235
5.20.2 Power OFF Sequence .......................................................................................................................................236
5.21 MTP WRITE SEQUENCE ..................................................................................................................................237
5.22 DYNAMIC BACKLIGHT CONTROL FUNCTION......................................................................................................238
5.22.1 PWM Control Architecture................................................................................................................................240
5.22.2 Dimming Function for LABC and Manual Brightness Control......................................................................245
5.22.3 Dimming Function for CABC and Force PWM Function................................................................................248
5.22.4 PWM Signal Setting for CABC and LABC .......................................................................................................249
5.22.5 Content Adaptive Brightness Control (CABC)................................................................................................251
5.22.6 Ambient Light Sensor and Automatic Brightness Control (LABC)...............................................................252
5.23
COLUMN, 1-DOT, 2-DOT, 3-DOT AND 4-DOT INVERSION (VCOM DC DRIVE).....................................................259
6 COMMAND DESCRIPTIONS ...........................................................................................................................260
6.1
USER COMMAND SET........................................................................................................................................260
NOP (0000h)..................................................................................................................................................................264
SWRESET: Software Reset (0100h) ............................................................................................................................265
RDDID: Read Display ID (0400h~0402h).....................................................................................................................266
RDNUMED: Read Number of Errors on DSI (0500h)..................................................................................................267
RDDPM: Read Display Power Mode (0A00h) .............................................................................................................268
RDDMADCTL: Read Display MADCTL (0B00h)..........................................................................................................269
RDDCOLMOD: Read Display Pixel Format (0C00h) ..................................................................................................270
RDDIM: Read Display Image Mode (0D00h) ...............................................................................................................271
RDDSM: Read Display Signal Mode (0E00h) .............................................................................................................272
RDDSDR: Read Display Self-Diagnostic Result (0F00h)...........................................................................................273
SLPIN: Sleep In (1000h) ...............................................................................................................................................274
PRELIMINARY NT35510
7/28/2010 5 Version 0.04
With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability,
fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such
information.
SLPOUT: Sleep Out (1100h).........................................................................................................................................276
PTLON: Partial Display Mode On (1200h) ..................................................................................................................278
NORON: Normal Display Mode On (1300h)................................................................................................................279
INVOFF: Display Inversion Off (2000h).......................................................................................................................280
INVON: Display Inversion On (2100h).........................................................................................................................281
ALLPOFF: All Pixel Off (2200h) ...................................................................................................................................282
ALLPON: All Pixel On (2300h).....................................................................................................................................284
GAMSET: Gamma Set (2600h).....................................................................................................................................286
DISPOFF: Display Off (2800h) .....................................................................................................................................287
DISPON: Display On (2900h) .......................................................................................................................................288
CASET: Column Address Set (2A00h~2A03h) ...........................................................................................................289
RASET: Row Address Set (2B00h~2B03h).................................................................................................................291
RAMWR: Memory Write (2C00h) .................................................................................................................................293
RAMRD: Memory Read (2E00h) ..................................................................................................................................294
PTLAR: Partial Area (3000h~3003h)............................................................................................................................295
TEOFF: Tearing Effect Line OFF (3400h)....................................................................................................................298
TEON: Tearing Effect Line ON (3500h) .......................................................................................................................299
MADCTL: Memory Data Access Control (3600h).......................................................................................................300
IDMOFF: Idle Mode Off (3800h)...................................................................................................................................303
IDMON: Idle Mode On (3900h).....................................................................................................................................304
COLMOD: Interface Pixel Format (3A00h)..................................................................................................................306
RAMWRC: Memory Write Continue (3C00h)..............................................................................................................307
RAMRDC: Memory Read Continue (3E00h) ...............................................................................................................308
STESL: Set Tearing Effect Scan Line (4400h~4401h)................................................................................................309
GSL: Get Scan Line (4500h~4501h)............................................................................................................................ 311
DPCKRGB: Display Clock in RGB Interface (4A00h) ................................................................................................312
DSTBON: Deep Standby Mode On (4F00h) ................................................................................................................313
WRPFD: Write Profile Value for Display (5000h~500Fh)...........................................................................................314
WRDISBV: Write Display Brightness (5100h) ............................................................................................................315
RDDISBV: Read Display Brightness (5200h) .............................................................................................................316
WRCTRLD: Write CTRL Display (5300h) ....................................................................................................................317
RDCTRLD: Read CTRL Display Value (5400h)...........................................................................................................319
WRCABC: Write Content Adaptive Brightness Control (5500h) ..............................................................................321
RDCABC: Read Content Adaptive Brightness Control (5600h) ...............................................................................322
WRHYSTE: Write Hysteresis (5700h~573Fh) .............................................................................................................323
