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October 2017 DocID14587 Rev 14 1/467

RM0016

Reference manual

STM8S Series and STM8AF Series 8-bit microcontrollers

Introduction

This reference manual provides complete information for application developers on how to

use STM8S Series and STM8AF Series microcontroller memory and peripherals.

The STM8AF Series of microcontrollers is designed for automotive applications, with

different memory densities, packages and peripherals:

• The low-density STM8AF devices are the STM8AF6223/26 with 8 Kbytes of Flash

memory.

• The medium-density STM8AF devices are the STM8AF624x and STM8AF6266/68

microcontrollers with 16 to 32 Kbytes of Flash memory.

• The high-density STM8AF devices are the STM8AF52xx and STM8AF6269/8x/Ax

microcontrollers with 32 to 128 Kbytes of Flash memory.

The STM8S Series of microcontrollers is designed for general purpose applications, with

different memory densities, packages and peripherals.

• The value-line low-density STM8S devices are the STM8S001xx/STM8S003xx

microcontrollers with 8 Kbytes of Flash memory.

• The value-line medium-density STM8S devices are the STM8S005xx microcontrollers

with 32 Kbytes of Flash memory.

• The value-line high-density STM8S devices are the STM8S007xx microcontrollers with

64 Kbytes of Flash memory.

• The access-line low-density STM8S devices are the STM8S103xx and STM8S903xx

microcontrollers with 8 Kbytes of Flash memory.

• The access-line medium-density STM8S devices are the STM8S105xx microcontrollers

with 16 to 32 Kbytes of Flash memory.

• The performance-line high-density STM8S devices are the STM8S207xx and

STM8S208xx microcontrollers with 32 to 128 Kbytes of Flash memory.

Refer to the product datasheet for ordering information, pin description, mechanical and

electrical device characteristics, and for the complete list of available peripherals.

Reference documents

• For information on programming, erasing and protection of the internal Flash memory

please refer to the STM8S Series and STM8AF Series Flash programming manual

(PM0051), and to the STM8 SWIM communication protocol and debug module user

manual (UM0470).

• For information on the STM8 core, refer to STM8 CPU programming manual (PM0044).

• The bootloader user manual (UM0560) describes the usage of the integrated ROM

bootloader.

www.st.com

Contents RM0016

2/467 DocID14587 Rev 14

Contents

1 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.1 CPU introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2.1 Description of CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.2.2 STM8 CPU register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.3 Global configuration register (CFG_GCR) . . . . . . . . . . . . . . . . . . . . . . . . 27

1.3.1 Activation level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.3.2 SWIM disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.3.3 Description of global configuration register (CFG_GCR) . . . . . . . . . . . . 28

1.3.4 Global configuration register map and reset values . . . . . . . . . . . . . . . 28

2 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1 Memory layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1.2 Stack handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2 Register description abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4 Flash program memory and data EEPROM . . . . . . . . . . . . . . . . . . . . . 34

4.1 Flash and EEPROM introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2 Flash and EEPROM glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3 Main Flash memory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.4.1 STM8S and STM8AF memory organization . . . . . . . . . . . . . . . . . . . . . 36

4.4.2 Memory access/ wait state configuration . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.3 User boot area (UBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.4 Data EEPROM (DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.4.5 Main program area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.4.6 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.5 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.5.1 Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.5.2 Memory access security system (MASS) . . . . . . . . . . . . . . . . . . . . . . . 44

DocID14587 Rev 14 3/467

RM0016 Contents

4.5.3 Enabling write access to option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.6 Memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.1 Read-while-write (RWW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.2 Byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6.3 Word programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6.4 Block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6.5 Option byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.7 ICP (in-circuit programming) and IAP (in-application programming) . . . . 49

4.8 Flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.8.1 Flash control register 1 (FLASH_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.8.2 Flash control register 2 (FLASH_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.8.3 Flash complementary control register 2 (FLASH_NCR2) . . . . . . . . . . . 53

4.8.4 Flash protection register (FLASH_FPR) . . . . . . . . . . . . . . . . . . . . . . . . 54

4.8.5 Flash protection register (FLASH_NFPR) . . . . . . . . . . . . . . . . . . . . . . . 54

4.8.6 Flash program memory unprotecting key register (FLASH_PUKR) . . . 54

4.8.7 Data EEPROM unprotection key register (FLASH_DUKR) . . . . . . . . . . 55

4.8.8 Flash status register (FLASH_IAPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.8.9 Flash register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5 Single wire interface module (SWIM) and debug module (DM) . . . . . 57

5.1 SWIM and DM introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2 SWIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3 SWIM modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6 Interrupt controller (ITC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.1 ITC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.2 Interrupt masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.2.1 Servicing pending interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.2.2 Interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.4 Activation level/low power mode control . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.5 Concurrent and nested interrupt management . . . . . . . . . . . . . . . . . . . . . 64

6.5.1 Concurrent interrupt management mode . . . . . . . . . . . . . . . . . . . . . . . . 64

6.5.2 Nested interrupt management mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.7 Interrupt instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Contents RM0016

4/467 DocID14587 Rev 14

6.8 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.9 ITC and EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.9.1 CPU condition code register interrupt bits (CCR) . . . . . . . . . . . . . . . . . 68

6.9.2 Software priority register x (ITC_SPRx) . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.9.3 External interrupt control register 1 (EXTI_CR1) . . . . . . . . . . . . . . . . . . 70

6.9.4 External interrupt control register 1 (EXTI_CR2) . . . . . . . . . . . . . . . . . . 71

6.9.5 ITC and EXTI register map and reset values . . . . . . . . . . . . . . . . . . . . . 72

7 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8 Reset (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.1 “Reset state” and “under reset” definitions . . . . . . . . . . . . . . . . . . . . . . . . 74

8.2 Reset circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.3 Internal reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.3.1 Power-on reset (POR) and brown-out reset (BOR) . . . . . . . . . . . . . . . . 75

8.3.2 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.3.3 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.3.4 SWIM reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.3.5 Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.3.6 EMC reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.4 RST register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.4.1 Reset status register (RST_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.5 RST register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9 Clock control (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.1 Master clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.1.1 HSE (high-speed external) clock signal . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.1.2 HSI (high-speed internal) clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.1.3 LSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9.2 Master clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.2.1 System startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.2.2 Master clock switching procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.3 Low-speed clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.4 CPU clock-divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

9.5 Peripheral clock-gating (PCG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

9.6 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

DocID14587 Rev 14 5/467

RM0016 Contents

9.7 Clock-out capability (CCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.8 CLK interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

9.9 CLK register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

9.9.1 Internal clock register (CLK_ICKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

9.9.2 External clock register (CLK_ECKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

9.9.3 Clock master status register (CLK_CMSR) . . . . . . . . . . . . . . . . . . . . . . 92

9.9.4 Clock master switch register (CLK_SWR) . . . . . . . . . . . . . . . . . . . . . . . 92

9.9.5 Switch control register (CLK_SWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.9.6 Clock divider register (CLK_CKDIVR) . . . . . . . . . . . . . . . . . . . . . . . . . . 94

9.9.7 Peripheral clock gating register 1 (CLK_PCKENR1) . . . . . . . . . . . . . . . 95

9.9.8 Peripheral clock gating register 2 (CLK_PCKENR2) . . . . . . . . . . . . . . . 96

9.9.9 Clock security system register (CLK_CSSR) . . . . . . . . . . . . . . . . . . . . . 97

9.9.10 Configurable clock output register (CLK_CCOR) . . . . . . . . . . . . . . . . . 98

9.9.11 HSI clock calibration trimming register (CLK_HSITRIMR) . . . . . . . . . . . 99

9.9.12 SWIM clock control register (CLK_SWIMCCR) . . . . . . . . . . . . . . . . . . . 99

9.10 CLK register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

10 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.1 General considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

10.1.1 Clock management for low consumption . . . . . . . . . . . . . . . . . . . . . . . 102

10.2 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

10.2.1 Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.2.2 Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.2.3 Active-halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

10.3 Additional analog power controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.3.1 Fast Flash wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

10.3.2 Very low Flash consumption in Active-halt mode . . . . . . . . . . . . . . . . . 104

11 General purpose I/O ports (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

11.3 Port configuration and usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

11.3.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

11.3.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.4 Reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

11.5 Unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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