AVR.zip_avr_iom1284p.h

/* Copyright (c) 2009 Atmel Corporation All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* $Id: iox128a1.h,v 1.1.2.17 2009/12/29 22:41:04 arcanum Exp $ */ /* avr/iox128a1.h - definitions for ATxmega128A1 */ /* This file should only be included from <avr/io.h>, never directly. */ #ifndef _AVR_IO_H_ # error "Include <avr/io.h> instead of this file." #endif #ifndef _AVR_IOXXX_H_ # define _AVR_IOXXX_H_ "iox128a1.h" #else # error "Attempt to include more than one <avr/ioXXX.h> file." #endif #ifndef _AVR_ATxmega128A1_H_ #define _AVR_ATxmega128A1_H_ 1 /* Ungrouped common registers */ #define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ #define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ #define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ #define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ #define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ #define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ #define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ #define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ #define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ #define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ #define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ #define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ #define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ #define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ #define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ #define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ #define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ #define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ #define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ #define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ #define SREG _SFR_MEM8(0x003F) /* Status Register */ /* C Language Only */ #if !defined (__ASSEMBLER__) #include <stdint.h> typedef volatile uint8_t register8_t; typedef volatile uint16_t register16_t; typedef volatile uint32_t register32_t; #ifdef _WORDREGISTER #undef _WORDREGISTER #endif #define _WORDREGISTER(regname) \ __extension__ union \ { \ register16_t regname; \ struct \ { \ register8_t regname ## L; \ register8_t regname ## H; \ }; \ } #ifdef _DWORDREGISTER #undef _DWORDREGISTER #endif #define _DWORDREGISTER(regname) \ __extension__ union \ { \ register32_t regname; \ struct \ { \ register8_t regname ## 0; \ register8_t regname ## 1; \ register8_t regname ## 2; \ register8_t regname ## 3; \ }; \ } /* ========================================================================== IO Module Structures ========================================================================== */ /* -------------------------------------------------------------------------- XOCD - On-Chip Debug System -------------------------------------------------------------------------- */ /* On-Chip Debug System */ typedef struct OCD_struct { register8_t OCDR0; /* OCD Register 0 */ register8_t OCDR1; /* OCD Register 1 */ } OCD_t; /* CCP signatures */ typedef enum CCP_enum { CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ } CCP_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Clock System */ typedef struct CLK_struct { register8_t CTRL; /* Control Register */ register8_t PSCTRL; /* Prescaler Control Register */ register8_t LOCK; /* Lock register */ register8_t RTCCTRL; /* RTC Control Register */ } CLK_t; /* -------------------------------------------------------------------------- CLK - Clock System -------------------------------------------------------------------------- */ /* Power Reduction */ typedef struct PR_struct { register8_t PRGEN; /* General Power Reduction */ register8_t PRPA; /* Power Reduction Port A */ register8_t PRPB; /* Power Reduction Port B */ register8_t PRPC; /* Power Reduction Port C */ register8_t PRPD; /* Power Reduction Port D */ register8_t PRPE; /* Power Reduction Port E */ register8_t PRPF; /* Power Reduction Port F */ } PR_t; /* System Clock Selection */ typedef enum CLK_SCLKSEL_enum { CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ } CLK_SCLKSEL_t; /* Prescaler A Division Factor */ typedef enum CLK_PSADIV_enum { CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ } CLK_PSADIV_t; /* Prescaler B and C Division Factor */ typedef enum CLK_PSBCDIV_enum { CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ } CLK_PSBCDIV_t; /* RTC Clock Source */ typedef enum CLK_RTCSRC_enum { CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal