LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BCD7 IS
PORT(a: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --数据输入
q : OUT STD_LOGIC_VECTOR(0 TO 6) ); --7 段输出
END BCD7;
ARCHITECTURE behav OF BCD7 IS
BEGIN
PROCESS (a)
BEGIN
case a(3 downto 0) is -- BCD 7 段译码表
when "0000" => q<="1111110"; when "0001" => q<="0110000";
when "0010" => q<="1101101 "; when "0011" => q<="1111001";
when "0100" => q<= "0110011"; when "0101" => q<="1011011";
when "0110" => q<="1011111"; when "0111" => q<="1110000";
when "1000" => q<="1111111"; when "1001" => q<="1111011";
when others => q<="0000000";
END case;
END PROCESS;
END behav;
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