/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ef4fb42 */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "G:/ISE/14.7/ISE_DS/ISE/verilog/src/glbl.v";
static unsigned int ng1[] = {1U, 0U};
static unsigned int ng2[] = {0U, 0U};
static void NetDecl_16_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
char *t10;
unsigned int t11;
unsigned int t12;
char *t13;
unsigned int t14;
unsigned int t15;
char *t16;
LAB0: t1 = (t0 + 3996U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(16, ng0);
t2 = (t0 + 1128U);
t3 = *((char **)t2);
t2 = (t0 + 4980);
t4 = (t2 + 32U);
t5 = *((char **)t4);
t6 = (t5 + 40U);
t7 = *((char **)t6);
memset(t7, 0, 8);
t8 = 1U;
t9 = t8;
t10 = (t3 + 4);
t11 = *((unsigned int *)t3);
t8 = (t8 & t11);
t12 = *((unsigned int *)t10);
t9 = (t9 & t12);
t13 = (t7 + 4);
t14 = *((unsigned int *)t7);
*((unsigned int *)t7) = (t14 | t8);
t15 = *((unsigned int *)t13);
*((unsigned int *)t13) = (t15 | t9);
xsi_driver_vfirst_trans(t2, 0, 0U);
t16 = (t0 + 4912);
*((int *)t16) = 1;
LAB1: return;
}
static void Cont_48_1(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
char *t12;
unsigned int t13;
unsigned int t14;
char *t15;
unsigned int t16;
unsigned int t17;
char *t18;
LAB0: t1 = (t0 + 4140U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(48, ng0);
t2 = (t0 + 2092);
t3 = (t2 + 36U);
t4 = *((char **)t3);
t5 = (t0 + 5016);
t6 = (t5 + 32U);
t7 = *((char **)t6);
t8 = (t7 + 40U);
t9 = *((char **)t8);
memset(t9, 0, 8);
t10 = 1U;
t11 = t10;
t12 = (t4 + 4);
t13 = *((unsigned int *)t4);
t10 = (t10 & t13);
t14 = *((unsigned int *)t12);
t11 = (t11 & t14);
t15 = (t9 + 4);
t16 = *((unsigned int *)t9);
*((unsigned int *)t9) = (t16 | t10);
t17 = *((unsigned int *)t15);
*((unsigned int *)t15) = (t17 | t11);
xsi_driver_vfirst_trans(t5, 0, 0);
t18 = (t0 + 4920);
*((int *)t18) = 1;
LAB1: return;
}
static void Cont_49_2(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
char *t12;
unsigned int t13;
unsigned int t14;
char *t15;
unsigned int t16;
unsigned int t17;
char *t18;
LAB0: t1 = (t0 + 4284U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(49, ng0);
t2 = (t0 + 2184);
t3 = (t2 + 36U);
t4 = *((char **)t3);
t5 = (t0 + 5052);
t6 = (t5 + 32U);
t7 = *((char **)t6);
t8 = (t7 + 40U);
t9 = *((char **)t8);
memset(t9, 0, 8);
t10 = 1U;
t11 = t10;
t12 = (t4 + 4);
t13 = *((unsigned int *)t4);
t10 = (t10 & t13);
t14 = *((unsigned int *)t12);
t11 = (t11 & t14);
t15 = (t9 + 4);
t16 = *((unsigned int *)t9);
*((unsigned int *)t9) = (t16 | t10);
t17 = *((unsigned int *)t15);
*((unsigned int *)t15) = (t17 | t11);
xsi_driver_vfirst_trans(t5, 0, 0);
t18 = (t0 + 4928);
*((int *)t18) = 1;
LAB1: return;
}
static void Cont_50_3(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
char *t12;
unsigned int t13;
unsigned int t14;
char *t15;
unsigned int t16;
unsigned int t17;
char *t18;
LAB0: t1 = (t0 + 4428U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(50, ng0);
t2 = (t0 + 2276);
t3 = (t2 + 36U);
t4 = *((char **)t3);
t5 = (t0 + 5088);
t6 = (t5 + 32U);
t7 = *((char **)t6);
t8 = (t7 + 40U);
t9 = *((char **)t8);
memset(t9, 0, 8);
t10 = 1U;
t11 = t10;
t12 = (t4 + 4);
t13 = *((unsigned int *)t4);
t10 = (t10 & t13);
t14 = *((unsigned int *)t12);
t11 = (t11 & t14);
t15 = (t9 + 4);
t16 = *((unsigned int *)t9);
*((unsigned int *)t9) = (t16 | t10);
t17 = *((unsigned int *)t15);
*((unsigned int *)t15) = (t17 | t11);
xsi_driver_vfirst_trans(t5, 0, 0);
t18 = (t0 + 4936);
*((int *)t18) = 1;
LAB1: return;
}
static void Initial_52_4(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
LAB0: t1 = (t0 + 4572U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(52, ng0);
LAB4: xsi_set_current_line(53, ng0);
t2 = ((char*)((ng1)));
t3 = (t0 + 2092);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
xsi_set_current_line(54, ng0);
t2 = ((char*)((ng1)));
t3 = (t0 + 2276);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
xsi_set_current_line(55, ng0);
t2 = (t0 + 4472);
xsi_process_wait(t2, 100000LL);
*((char **)t1) = &&LAB5;
LAB1: return;
LAB5: xsi_set_current_line(56, ng0);
t3 = ((char*)((ng2)));
t4 = (t0 + 2092);
xsi_vlogvar_assign_value(t4, t3, 0, 0, 1);
xsi_set_current_line(57, ng0);
t2 = ((char*)((ng2)));
t3 = (t0 + 2276);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
goto LAB1;
}
static void Initial_60_5(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
LAB0: t1 = (t0 + 4716U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(60, ng0);
LAB4: xsi_set_current_line(61, ng0);
t2 = ((char*)((ng1)));
t3 = (t0 + 2184);
xsi_vlogvar_assign_value(t3, t2, 0, 0, 1);
xsi_set_current_line(62, ng0);
t2 = (t0 + 4616);
xsi_process_wait(t2, 0LL);
*((char **)t1) = &&LAB5;
LAB1: return;
LAB5: xsi_set_current_line(63, ng0);
t3 = ((char*)((ng2)));
t4 = (t0 + 2184);
xsi_vlogvar_assign_value(t4, t3, 0, 0, 1);
goto LAB1;
}
extern void work_m_00000000004134447467_2073120511_init()
{
static char *pe[] = {(void *)NetDecl_16_0,(void *)Cont_48_1,(void *)Cont_49_2,(void *)Cont_50_3,(void *)Initial_52_4,(void *)Initial_60_5};
xsi_register_didat("work_m_00000000004134447467_2073120511", "isim/seq_test_isim_beh.exe.sim/work/m_00000000004134447467_2073120511.didat");
xsi_register_executes(pe);
}
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ALU.rar_32bit alu_Alu_u32_alu_斐波那契数列_算术逻辑单元 (100个子文件)
_1 7KB
_1 3KB
_a_l_u.bin 4KB
_fibo__seq.bin 3KB
m_00000000004134447467_2073120511.c 8KB
m_00000000004134447467_2073120511.c 8KB
m_00000000001883506334_0886308060.c 6KB
m_00000000001883506334_0886308060.c 6KB
m_00000000003263290149_2251718801.c 5KB
m_00000000002544648423_2856494725.c 5KB
m_00000000001195913962_2880621034.c 3KB
seq_test_isim_beh.exe_main.c 1KB
ALU_test_isim_beh.exe_main.c 1KB
fuseRelaunch.cmd 246B
isim.cmd 44B
ALU.cmd_log 366B
Fibo_seq.cmd_log 132B
netId1.dat 68B
netId.dat 68B
netId1.dat 52B
ISimEngine-DesignHierarchy1.dbg 8KB
ISimEngine-DesignHierarchy1.dbg 5KB
ISimEngine-DesignHierarchy.dbg 5KB
m_00000000003263290149_2251718801.didat 5KB
m_00000000004134447467_2073120511.didat 5KB
m_00000000004134447467_2073120511.didat 5KB
m_00000000001883506334_0886308060.didat 3KB
m_00000000002544648423_2856494725.didat 3KB
m_00000000001883506334_0886308060.didat 3KB
m_00000000001195913962_2880621034.didat 3KB
seq_test_isim_beh.exe 81KB
ALU_test_isim_beh.exe 81KB
ALU_test_isim_beh.exe 25KB
seq_test_isim_beh.exe 25KB
Lab01_ALU.gise 9KB
Fibo_seq_envsettings.html 8KB
ALU_envsettings.html 8KB
Fibo_seq_summary.html 5KB
ALU_summary.html 5KB
isim_usage_statistics.html 2KB
xilinxsim.ini 16B
fuse.log 1KB
isim.log 878B
isimkernel.log 568B
isimkernel.log 564B
isimcrash.log 0B
isimcrash.log 0B
ALU.lso 6B
.lso 6B
Fibo_seq.lso 6B
Fibo_seq.ngc 68KB
ALU.ngc 50KB
ALU.ngr 107KB
Fibo_seq.ngr 83KB
m_00000000002544648423_2856494725.nt.obj 3KB
m_00000000001883506334_0886308060.nt.obj 3KB
m_00000000001883506334_0886308060.nt.obj 3KB
m_00000000004134447467_2073120511.nt.obj 3KB
m_00000000004134447467_2073120511.nt.obj 3KB
m_00000000001195913962_2880621034.nt.obj 2KB
m_00000000003263290149_2251718801.nt.obj 2KB
seq_test_isim_beh.exe_main.nt.obj 1KB
ALU_test_isim_beh.exe_main.nt.obj 1KB
pn_info 6B
seq_test_beh.prj 135B
ALU_test_stx_beh.prj 123B
Fibo_seq.prj 49B
ALU.prj 22B
Lab01_ALU.projectmgr 7KB
hdllib.ref 108B
glbl.sdb 4KB
glbl.sdb 4KB
@a@[email protected] 3KB
@a@[email protected] 3KB
@a@l@u_test.sdb 2KB
@fibo_seq.sdb 2KB
seq_test.sdb 1KB
ALU.stx 1KB
Fibo_seq.stx 0B
Fibo_seq.syr 36KB
ALU.syr 17KB
ALU_test.v 1KB
ALU.v 1KB
seq_test.v 1KB
Fibo_seq.v 706B
seq_test_isim_beh1.wdb 9KB
ALU_test_isim_beh1.wdb 8KB
ALU_test_isim_beh.wdb 144B
seq_test_isim_beh.wdb 0B
Lab01_ALU.xise 39KB
webtalk_pn.xml 3KB
xst.xmsgs 50KB
pn_parser.xmsgs 762B
fuse.xmsgs 367B
ALU.xreport 20KB
Fibo_seq.xreport 20KB
ALU_xst.xrpt 10KB
Fibo_seq_xst.xrpt 10KB
Fibo_seq.xst 1KB
ALU.xst 163B
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