Qualcomm SuperSpeed DWC3 USB SoC controller
Required properties:
- compatible: should contain "qcom,dwc3"
- clocks: A list of phandle + clock-specifier pairs for the
clocks listed in clock-names
- clock-names: Should contain the following:
"core" Master/Core clock, have to be >= 125 MHz for SS
operation and >= 60MHz for HS operation
Optional clocks:
"iface" System bus AXI clock. Not present on all platforms
"sleep" Sleep clock, used when USB3 core goes into low
power mode (U3).
Required child node:
A child node must exist to represent the core DWC3 IP block. The name of
the node is not important. The content of the node is defined in dwc3.txt.
Phy documentation is provided in the following places:
Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
Example device nodes:
hs_phy: phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>;
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "ok";
};
ss_phy: phy@100f8830 {
compatible = "qcom,dwc3-ss-usb-phy";
reg = <0x100f8830 0x30>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "ok";
};
usb3_0: usb30@0 {
compatible = "qcom,dwc3";
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core";
ranges;
status = "ok";
dwc3@10000000 {
compatible = "snps,dwc3";
reg = <0x10000000 0xcd00>;
interrupts = <0 205 0x4>;
phys = <&hs_phy>, <&ss_phy>;
phy-names = "usb2-phy", "usb3-phy";
tx-fifo-resize;
dr_mode = "host";
};
};
qcom-dwc3.rar_SOC
版权申诉
118 浏览量
2022-09-23
00:52:30
上传
评论
收藏 2KB RAR 举报
局外狗
- 粉丝: 65
- 资源: 1万+
最新资源
- 【kettle012】kettle访问FTP服务器文件并处理数据至PostgreSQL
- MTXX_MR20240511_001342250.jpg
- base.apk
- kettle访问PostgreSQL数据库并处理数据至execl文件环境搭建材料
- 2023-04-06-项目笔记 - 第一百二十九阶段 - 4.4.2.127全局变量的作用域-127 -2024.05.10
- STM32F103C8T6控制L298N驱动直流电机(有代码)
- 123123123123123
- Screenshot_20240509_145753.jpg
- 实验8_任务指导书_任务指导书.zip
- STM32开发过程中常用的C语言知识点
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈