DS718 April 19, 2010 www.xilinx.com 1
Product Specification
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v
Introduction
The LogiCORE™ IP Spartan®-6 FPGA Integrated End-
point Block for PCI Express
® core is a high-bandwidth,
scalable, and reliable serial interconnect building block
for use with Spartan-6 FPGA devices. The Spartan-6
FPGA Integrated Endpoint Block for PCI Express
(PCIe®) solution supports a 1-lane configuration that is
protocol-compliant and electrically compatible with the
PCI Express Base Specification v1.1.
PCI Express offers a serial architecture that alleviates
many of the limitations of parallel bus architectures by
using clock data recovery (CDR) and differential signal-
ing. Using CDR (as opposed to source synchronous
clocking) lowers pin count, enables superior frequency
scalability, and makes data synchronization easier. The
layered architecture of PCI Express provides for future
attachment to copper, optical, or emerging physical sig-
naling media. PCI Express technology, adopted by the
PCI-SIG as the next generation PCI, is backward-com-
patible to the existing PCI software model.
With higher bandwidth per pin, low overhead, low
latency, reduced signal integrity issues, and CDR archi-
tecture, the Integrated Endpoint Block sets the industry
standard for a high-performance, cost-efficient third-
generation I/O solution.
The Integrated Endpoint Block solution is compatible
with industry-standard application form factors such
as the PCI Express Card Electromechanical (CEM) v1.1
and the PCI Industrial Computer Manufacturers Group
(PICMG) 3.4 specifications.
This core is defined in the following table.
LogiCORE IP Spartan-6 FPGA
Integrated Endpoint Block
v1.3 for PCI Express
DS718 April 19, 2010 Product Specification
Product Name 1-lane Integrated Endpoint Block
FPGA Architecture Spartan-6
User Interface Width 32
Lane Widths Supported x1
Link Speeds Supported 2.5 GT/s
PCIe Base Specification
Compliance
v1.1
LogiCORE IP Facts
Core Specifics
Supported FPGA
Device Families
(1)
1. For the complete list of supported devices, see the 12.1 release
notes for this core.
Spartan-6
(2)
2. Spartan-6 FPGA solutions require the latest production silicon step-
ping and are pending hardware validation; the LogiCOR
E IP w
arran-
ty does not include production usage with engineering sample
silicon (ES).
Min. Device
Requirements
XC6SLX25T-CSG324-2
Resources Used
I/O
(3)
3. GTP transceivers.
LUT
(4)
4. Numbers are for the default core configuration; actual LUT and FF
utilization values vary based on specific configurations.
FF
(3)
1
(5)
5. In Spartan-6 devices, 1-lane Endpoint core uses 1 GTP tile (2 GTP
transceivers). It is possible to use the other GTP transceiver for user
designs with some limitations.
30
Block RAM
CMPS
(6)
# Tx
Buffers
6. Capability Maximum Payload Size (CMPS).
CMPS
2-18 30
(7)
7. Supports 30 TLPs at CMPS (512 bytes payload): No restrictions.
- Supports 29 TLPs at 256 bytes payload: No restrictions.
- Supports 27 TLPs at 128 bytes payload or less: No restrictions.
512
Special Features
GTP Transceivers
Spartan-6 FPGA Integrated Block for PCI
Express
Phased Lock Loop
Block RAM
Provided with Core
Documentation
Product Specification,
User Guide, Instantiation Template
Design Files
Verilog and VHDL Unencrypted RTL source files
for Simulation and Synthesis,
Verilog and VHDL Test Bench,
Verilog and VHDL Example Design
Constraints File
User Constraints File (UCF)
Design Tool Support
HDL Synthesis Tool
Synplicity® Synplify®, Xilinx XST
Implementation
Tools
Xilinx ISE® v12.1
Simulation Tools
(8)
8. Requires a Verilog LRM-IEEE 1364-2005 encryption-compliant
simulator.
Cadence® Incisive Enterprise Simulator (IES)
v9.2 and above
Synopsys® VCS and VCS MX 2009.12 and above
Mentor Graphics® ModelSim® v6.5c and above
Support
Provided by Xilinx, Inc. @
www.xilinx.com/support
