hainan.rar_VHDL hainan

library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fengxi is port( reset,adjust,clk:in std_logic; y:out std_logic_vector(9 downto 0)); end; architecture behaviol of fengxi is signal count:integer range 0 to 6000;--计数器,分频成豪秒 signal millisecond1,millisecond2:integer range 0 to 500;--分频成,秒 signal second1,second2:std_logic;--1S,0.5 S signal countclk:std_logic;--状态机触发时钟 signal y_out:std_logic_vector(9 downto 0); type states is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11, s12,s13,s14,s15,s16,s17,s18,s19,s20,S21);--状态生成,将所需变化以状态机形式输出 signal state:states; begin process(CLK,RESET) begin if RESET='1' then count<=0;second1<='0';second2<='0'; elsif CLK'event and CLK='1' then count<=count+1;--毫秒,可调变成自己想要的时钟 if count=6000 then millisecond1<=millisecond1+1; millisecond2<=millisecond2+1; count<=0; end if; if millisecond1=500 then--1S可调变成自己想要的时钟 second1<=not second1; millisecond1<=0; end if; if millisecond2=250 then--0.5S可调变成自己想要的时钟 second2<=not second2; millisecond2<=0; end if; end if; end process; process(adjust,reset)--调速 begin if (reset='1') then countclk<='0';else if adjust='1' then countclk<=second1;end if; if adjust='0' then countclk<=second2;end if; end if; end process; process(reset)--状态转移 begin if (reset='1') then state<=s0;else if(rising_edge(countclk)) then case state is when s0 =>state<=s1; when s1=>state<=s2; when s2=>state<=s3; when s3 =>state<=s4; when s4=>state<=s5; when s5=>state<=s6; when s6=>state<=s7; when s7 =>state<=s8; when s8=>state<=s9; when s9=>state<=s10; when s10 =>state<=s11; when s11=>state<=s12; when s12=>state<=s13; when s13=>state<=s14; when s14 =>state<=s15; when s15=>state<=s16; when s16=>state<=s17; when s17 =>state<=s18; when s18=>state<=s19; when s19=>state<=s20; when s20=>state<=s21; WHEN S21=>STATE<=S0; end case; end if; end if; end process; process(reset)--状态赋值输出 begin if reset='1' then y_out<="1111111111"; else case state is when s0=>y_out<="1111111111"; when s1=>y_out<="0111111111"; when s2=>y_out<="0101111111"; when s3=>y_out<="0101011111"; when s4=>y_out<="0101010111"; when s5=>y_out<="0101010101"; when s6=>y_out<="1111111111"; when s7=>y_out<="1011111111"; when s8=>y_out<="1010111111"; when s9=>y_out<="1010101111"; when s10=>y_out<="1010101011"; when s11=>y_out<="1010101010"; when s12=>y_out<="1111111111"; when s13=>y_out<="0111111111"; when s14=>y_out<="0011111111"; when s15=>y_out<="0001111111"; when s16=>y_out<="0000111111"; when s17=>y_out<="0000011111"; when s18=>y_out<="0000001111"; when s19=>y_out<="0000000111"; when s20=>y_out<="0000000011"; when s21 =>y_out<="0000000001"; when others=>y_out<="ZZZZZZZZZZ"; end case; end if; y<=y_out; end process; end;