/******************************************************************************
FILE : datapage.c
PURPOSE : paged data access runtime routines
MACHINE : Freescale 68HC12 (Target)
LANGUAGE : ANSI-C
HISTORY : 21.7.96 first version created
******************************************************************************/
#include "hidef.h"
#include "non_bank.sgm"
#include "runtime.sgm"
#ifndef __HCS12X__ /* it's different for the HCS12X. See the text below at the #else // __HCS12X__ */
/*
According to the -Cp option of the compiler the
__DPAGE__, __PPAGE__ and __EPAGE__ macros are defined.
If none of them is given as argument, then no page accesses should occur and
this runtime routine should not be used !
To be on the save side, the runtime routines are created anyway.
If some of the -Cp options are given an adapted versions which only covers the
needed cases is produced.
*/
/* if no compiler option -Cp is given, it is assumed that all possible are given : */
/* Compile with option -DHCS12 to activate this code */
#if defined(HCS12) || defined(_HCS12) || defined(__HCS12__) /* HCS12 family has PPAGE register only at 0x30 */
#define PPAGE_ADDR (0x30+REGISTER_BASE)
#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */
#define __PPAGE__
#endif
/* Compile with option -DDG128 to activate this code */
#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */
#define PPAGE_ADDR (0xFF+REGISTER_BASE)
#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */
#define __PPAGE__
#endif
#elif defined(HC812A4)
/* all setting default to A4 already */
#endif
#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__)
/* as default use all page registers */
#define __DPAGE__
#define __EPAGE__
#define __PPAGE__
#endif
/* modify the following defines to your memory configuration */
#define EPAGE_LOW_BOUND 0x400u
#define EPAGE_HIGH_BOUND 0x7ffu
#define DPAGE_LOW_BOUND 0x7000u
#define DPAGE_HIGH_BOUND 0x7fffu
#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1)
#define PPAGE_HIGH_BOUND 0xBFFFu
#define REGISTER_BASE 0x0u
#ifndef DPAGE_ADDR
#define DPAGE_ADDR (0x34u+REGISTER_BASE)
#endif
#ifndef EPAGE_ADDR
#define EPAGE_ADDR (0x36u+REGISTER_BASE)
#endif
#ifndef PPAGE_ADDR
#define PPAGE_ADDR (0x35u+REGISTER_BASE)
#endif
/*
The following parts about the defines are assumed in the code of _GET_PAGE_REG :
- the memory region controlled by DPAGE is above the area controlled by the EPAGE and
below the area controlled by the PPAGE.
- the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1
*/
#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND
#error /* please adapt _GET_PAGE_REG for this non default page configuration */
#endif
#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND
#error /* please adapt _GET_PAGE_REG for this non default page configuration */
#endif
/* this module does either control if any access is in the bounds of the specified page or */
/* ,if only one page is specified, just use this page. */
/* This behavior is controlled by the define USE_SEVERAL_PAGES. */
/* If !USE_SEVERAL_PAGES does increase the performance significantly */
/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */
/* by this single page. But this is should not cause problems because the page is restored to the old value before any other access could occur */
#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__)
/* no page at all is specified */
/* only specifying the right pages will speed up these functions a lot */
#define USE_SEVERAL_PAGES 1
#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__)
/* more than one page register is used */
#define USE_SEVERAL_PAGES 1
#else
#define USE_SEVERAL_PAGES 0
#if defined(__DPAGE__) /* check which pages are used */
#define PAGE_ADDR PPAGE_ADDR
#elif defined(__EPAGE__)
#define PAGE_ADDR EPAGE_ADDR
#elif defined(__PPAGE__)
#define PAGE_ADDR PPAGE_ADDR
#else /* we do not know which page, decide it at runtime */
#error /* must not happen */
#endif
#endif
#if USE_SEVERAL_PAGES /* only needed for several pages support */
/*--------------------------- _GET_PAGE_REG --------------------------------
Runtime routine to detect the right register depending on the 16 bit offset part
of an address.
This function is only used by the functions below.
Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced.
Arguments :
- Y : offset part of an address
Result :
if address Y is controlled by a page register :
- X : address of page register if Y is controlled by an page register
- Zero flag cleared
- all other registers remain unchanged
if address Y is not controlled by a page register :
- Zero flag is set
- all registers remain unchanged
--------------------------- _GET_PAGE_REG ----------------------------------*/
#if defined(__DPAGE__)
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */
__asm {
L_DPAGE:
CPY #DPAGE_LOW_BOUND ;// test of lower bound of DPAGE
#if defined(__EPAGE__)
BLO L_EPAGE ;// EPAGE accesses are possible
#else
BLO L_NOPAGE ;// no paged memory below accesses
#endif
CPY #DPAGE_HIGH_BOUND ;// test of higher bound DPAGE/lower bound PPAGE
#if defined(__PPAGE__)
BHI L_PPAGE ;// EPAGE accesses are possible
#else
BHI L_NOPAGE ;// no paged memory above accesses
#endif
FOUND_DPAGE:
LDX #DPAGE_ADDR ;// load page register address and clear zero flag
RTS
#if defined(__PPAGE__)
L_PPAGE:
CPY #PPAGE_HIGH_BOUND ;// test of higher bound of PPAGE
BHI L_NOPAGE
FOUND_PPAGE:
LDX #PPAGE_ADDR ;// load page register address and clear zero flag
RTS
#endif
#if defined(__EPAGE__)
L_EPAGE:
CPY #EPAGE_LOW_BOUND ;// test of lower bound of EPAGE
BLO L_NOPAGE
CPY #EPAGE_HIGH_BOUND ;// test of higher bound of EPAGE
BHI L_NOPAGE
FOUND_EPAGE:
LDX #EPAGE_ADDR ;// load page register address and clear zero flag
RTS
#endif
L_NOPAGE:
ORCC #0x04 ;// sets zero flag
RTS
}
}
#else /* !defined(__DPAGE__) */
#if defined( __PPAGE__ )
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */
__asm {
L_PPAGE:
CPY #PPAGE_LOW_BOUND ;// test of lower bound of PPAGE
#if defined( __EPAGE__ )
BLO L_EPAGE
#else
BLO L_NOPAGE ;// no paged memory below
#endif
CPY #PPAGE_HIGH_BOUND ;// test of higher bound PPAGE
BHI L_NOPAGE
FOUND_PPAGE:
LDX #PPAGE_ADDR ;// load page register address and clear zero flag
RTS
#if defined( __EPAGE__ )
L_EPAGE:
CPY #EPAGE_LOW_BOUND ;// test of lower bound of EPAGE
BLO L_NOPAGE
CPY #EPAGE_HIGH_BOUND ;// test of higher bound of EPAGE
BHI L_NOPAGE
FOUND_EPAGE:
LDX #EPAGE_ADDR ;// load page register address and clear zero flag
RTS
#endif
L_NOPAGE: ;// not in any allowed page area
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sci.rar_MC9S12X_MC9S12X sci
共108个文件
cmd:28个
o:16个
c:12个
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sci.rar_MC9S12X_MC9S12X sci (108个子文件)
Project.abs 160KB
Project.abs 160KB
Project.abs 160KB
Project.abs 160KB
burner.bbl 10KB
burner.bbl 10KB
burner.bbl 10KB
burner.bbl 10KB
datapage.c 67KB
datapage.c 67KB
datapage.c 67KB
datapage.c 67KB
Start12.c 22KB
Start12.c 22KB
Start12.c 22KB
Start12.c 22KB
main.c 3KB
main.c 3KB
main.c 3KB
main.c 3KB
TBDML_Erase_unsecure_hcs12xe.cmd 1KB
TBDML_Erase_unsecure_hcs12xe.cmd 1KB
TBDML_Erase_unsecure_hcs12xe.cmd 1KB
TBDML_Erase_unsecure_hcs12xe.cmd 1KB
TBDML_Vppon.cmd 78B
TBDML_Vppon.cmd 78B
TBDML_Vppon.cmd 78B
TBDML_Vppon.cmd 78B
TBDML_Vppoff.cmd 77B
TBDML_Vppoff.cmd 77B
TBDML_Vppoff.cmd 77B
TBDML_Vppoff.cmd 77B
TBDML_Preload.cmd 60B
TBDML_Reset.cmd 60B
TBDML_Preload.cmd 60B
TBDML_Reset.cmd 60B
TBDML_Reset.cmd 60B
TBDML_Reset.cmd 60B
TBDML_Preload.cmd 60B
TBDML_Preload.cmd 60B
TBDML_Postload.cmd 59B
TBDML_Startup.cmd 59B
TBDML_Postload.cmd 59B
TBDML_Startup.cmd 59B
TBDML_Postload.cmd 59B
TBDML_Startup.cmd 59B
TBDML_Startup.cmd 59B
TBDML_Postload.cmd 59B
Project.abs.glo 776B
Project.abs.glo 742B
Project.abs.glo 702B
Project.abs.glo 686B
derivative.h 262B
derivative.h 262B
derivative.h 262B
derivative.h 262B
C_Layout.hwl 855B
C_Layout.hwl 855B
C_Layout.hwl 855B
C_Layout.hwl 855B
TBDML.ini 3KB
TBDML.ini 2KB
TBDML.ini 2KB
TBDML.ini 2KB
Project.map 97KB
Project.map 97KB
Project.map 97KB
Project.map 96KB
SCI_receive_zhongduan.mcp 57KB
SCI_send_chaxun.mcp 57KB
SCI_receive_chaxun.mcp 57KB
SCI_send_zhongduan.mcp 57KB
Default.mem 161B
Default.mem 161B
Default.mem 161B
Default.mem 161B
MC9S12XS128.c.o 161KB
MC9S12XS128.c.o 161KB
MC9S12XS128.c.o 161KB
MC9S12XS128.c.o 161KB
datapage.c.o 14KB
datapage.c.o 14KB
datapage.c.o 14KB
datapage.c.o 14KB
main.c.o 13KB
main.c.o 13KB
main.c.o 13KB
main.c.o 13KB
Start12.c.o 6KB
Start12.c.o 6KB
Start12.c.o 6KB
Start12.c.o 6KB
Project.prm 6KB
Project.prm 6KB
Project.prm 6KB
Project.prm 6KB
Project.abs.s19 766B
Project.abs.s19 736B
Project.abs.s19 694B
Project.abs.s19 682B
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