DSP_FFT.rar_dsp_https//:1024dsp.com_stm32 dsp库_stm32f0xdsp_基于stm

/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** * File Name : stm32f10x_tim.c * Author : MCD Application Team * Version : V2.0.3 * Date : 09/22/2008 * Description : This file provides all the TIM firmware functions. ******************************************************************************** * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *******************************************************************************/ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_tim.h" #include "stm32f10x_rcc.h" /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ---------------------- TIM registers bit mask ------------------------ */ #define CR1_CEN_Set ((u16)0x0001) #define CR1_CEN_Reset ((u16)0x03FE) #define CR1_UDIS_Set ((u16)0x0002) #define CR1_UDIS_Reset ((u16)0x03FD) #define CR1_URS_Set ((u16)0x0004) #define CR1_URS_Reset ((u16)0x03FB) #define CR1_OPM_Reset ((u16)0x03F7) #define CR1_CounterMode_Mask ((u16)0x038F) #define CR1_ARPE_Set ((u16)0x0080) #define CR1_ARPE_Reset ((u16)0x037F) #define CR1_CKD_Mask ((u16)0x00FF) #define CR2_CCPC_Set ((u16)0x0001) #define CR2_CCPC_Reset ((u16)0xFFFE) #define CR2_CCUS_Set ((u16)0x0004) #define CR2_CCUS_Reset ((u16)0xFFFB) #define CR2_CCDS_Set ((u16)0x0008) #define CR2_CCDS_Reset ((u16)0xFFF7) #define CR2_MMS_Mask ((u16)0xFF8F) #define CR2_TI1S_Set ((u16)0x0080) #define CR2_TI1S_Reset ((u16)0xFF7F) #define CR2_OIS1_Reset ((u16)0x7EFF) #define CR2_OIS1N_Reset ((u16)0x7DFF) #define CR2_OIS2_Reset ((u16)0x7BFF) #define CR2_OIS2N_Reset ((u16)0x77FF) #define CR2_OIS3_Reset ((u16)0x6FFF) #define CR2_OIS3N_Reset ((u16)0x5FFF) #define CR2_OIS4_Reset ((u16)0x3FFF) #define SMCR_SMS_Mask ((u16)0xFFF8) #define SMCR_ETR_Mask ((u16)0x00FF) #define SMCR_TS_Mask ((u16)0xFF8F) #define SMCR_MSM_Reset ((u16)0xFF7F) #define SMCR_ECE_Set ((u16)0x4000) #define CCMR_CC13S_Mask ((u16)0xFFFC) #define CCMR_CC24S_Mask ((u16)0xFCFF) #define CCMR_TI13Direct_Set ((u16)0x0001) #define CCMR_TI24Direct_Set ((u16)0x0100) #define CCMR_OC13FE_Reset ((u16)0xFFFB) #define CCMR_OC24FE_Reset ((u16)0xFBFF) #define CCMR_OC13PE_Reset ((u16)0xFFF7) #define CCMR_OC24PE_Reset ((u16)0xF7FF) #define CCMR_OC13M_Mask ((u16)0xFF8F) #define CCMR_OC24M_Mask ((u16)0x8FFF) #define CCMR_OC13CE_Reset ((u16)0xFF7F) #define CCMR_OC24CE_Reset ((u16)0x7FFF) #define CCMR_IC13PSC_Mask ((u16)0xFFF3) #define CCMR_IC24PSC_Mask ((u16)0xF3FF) #define CCMR_IC13F_Mask ((u16)0xFF0F) #define CCMR_IC24F_Mask ((u16)0x0FFF) #define CCMR_Offset ((u16)0x0018) #define CCER_CCE_Set ((u16)0x0001) #define CCER_CCNE_Set ((u16)0x0004) #define CCER_CC1P_Reset ((u16)0xFFFD) #define CCER_CC2P_Reset ((u16)0xFFDF) #define CCER_CC3P_Reset ((u16)0xFDFF) #define CCER_CC4P_Reset ((u16)0xDFFF) #define CCER_CC1NP_Reset ((u16)0xFFF7) #define CCER_CC2NP_Reset ((u16)0xFF7F) #define CCER_CC3NP_Reset ((u16)0xF7FF) #define CCER_CC1E_Set ((u16)0x0001) #define CCER_CC1E_Reset ((u16)0xFFFE) #define CCER_CC1NE_Reset ((u16)0xFFFB) #define CCER_CC2E_Set ((u16)0x0010) #define CCER_CC2E_Reset ((u16)0xFFEF) #define CCER_CC2NE_Reset ((u16)0xFFBF) #define CCER_CC3E_Set ((u16)0x0100) #define CCER_CC3E_Reset ((u16)0xFEFF) #define CCER_CC3NE_Reset ((u16)0xFBFF) #define CCER_CC4E_Set ((u16)0x1000) #define CCER_CC4E_Reset ((u16)0xEFFF) #define BDTR_MOE_Set ((u16)0x8000) #define BDTR_MOE_Reset ((u16)0x7FFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, u16 TIM_ICFilter); static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, u16 TIM_ICFilter); static void TI3_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, u16 TIM_ICFilter); static void TI4_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection, u16 TIM_ICFilter); /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /******************************************************************************* * Function Name : TIM_DeInit * Description : Deinitializes the TIMx peripheral registers to their default * reset values. * Input : - TIMx: where x can be 1 to 8 to select the TIM peripheral. * Output : None * Return : None *******************************************************************************/ void TIM_DeInit(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); switch (*(u32*)&TIMx) { case TIM1_BASE: RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); break; case TIM2_BASE: RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); break; case TIM3_BASE: RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); break; case TIM4_BASE: RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); break; case TIM5_BASE: RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); break; case TIM6_BASE: RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); break; case TIM7_BASE: RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); break; case TIM8_BASE: RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); break; default: break; } } /*************