Advanced Encryption
Standard / Rijndael
IP Core
Author: Rudolf Usselmann
rudi@asics.ws
www.asics.ws
Rev. 1.1
November 12, 2002
Revision History
Rev. Date Author Description
1.0 11/9/02 Rudolf
Usselmann
Initial Release
1.1 11/12/2002 RU Fixed Several Typos
ASICS.ws AES Rijndael IP Core November 12, 2002
www.asics.ws Rev. 1.1 1 of 9
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Introduction
Simple AES/Rijndael IP Core. I have tried to create a implementation of this
standard that would fit in to a low cost FPGA, like the Spartan IIe series from Xil-
inx, and still would provide reasonably fast performance.
This implementation is with a 128 bit key expansion module only. Implementa-
tions with different key sizes (192 & 256 bits) and performance parameters (such
as a fully pipelined ultra-high -speed version) are commercially available from
ASICS.ws (www.asics.ws).
This document will describe the interface to the IP core. It will not talk about
the AES standard itself.
November 12, 2002 AES Rijndael IP Core ASICS.ws
2 of 9 Rev. 1.1 www.asics.ws
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