//###########################################################################
// $TI Release: DSP2833x/DSP2823x Header Files V1.20 $
// $Release Date: August 1, 2008 $
//###########################################################################
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "DSP2833x_EPwm_defines.h" // useful defines for initialization
// Declare your function prototypes here
//---------------------------------------------------------------
void JCQGpio(void);
void SW_Gpio(void);
void Delay(unsigned int);
void HRPWM1_Config(int);
void HRPWM2_Config(int);
void HRPWM3_Config(int);
void HRPWM4_Config(int);
void key_judge(void);
void pwm_control(unsigned int);
void AD_Gpio(void);
void AD_convert(void);
void PIDControl(Uint32 MXU,Uint32 MXI);
interrupt void cpu_timer0_isr(void);
#define AD_DATA *(unsigned int *)0x100000
#define startCpuTimer0() CpuTimer0Regs.TCR.bit.TSS=0
// General System nets - Useful for debug
Uint16 i,j,DutyFine,n,update,DutyFine1,DutyFine2,flag,swon,swoff,flag1,ADstart;
Uint32 MXI,MXU,temp[6];
int PWM_count,PWM_max,PWM_min;
float MXU_M,MXI_M,Uref,Ek_U,Ek1_U,U_Uk,UpU_max,UpU_min,Ek_I,Ek1_I,I_Uk,Kp_U,Kp_I,Ki_U,Ki_I,HE,HF;
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// For this case, just init GPIO for ePWM1-ePWM4
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4
// These functions are in the DSP2833x_EPwm.c file
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
// InitEPwm4Gpio();
JCQGpio();
SW_Gpio();
AD_Gpio();
AD_convert();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
InitXintf16Gpio();
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.TINT0 = &cpu_timer0_isr;
//PieVectTable.XINT13 = &cpu_timer1_isr;
//PieVectTable.TINT2 = &cpu_timer2_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
InitCpuTimers(); // For this example, only initialize the Cpu Timers
#if (CPU_FRQ_150MHZ)
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 150MHz CPU Freq, 1 second Period (in uSeconds)
ConfigCpuTimer(&CpuTimer0, 150, 1000000);
//ConfigCpuTimer(&CpuTimer1, 150, 1000000);
//ConfigCpuTimer(&CpuTimer2, 150, 1000000);
#endif
#if (CPU_FRQ_100MHZ)
// Configure CPU-Timer 0, 1, and 2 to interrupt every second:
// 100MHz CPU Freq, 1 second Period (in uSeconds)
ConfigCpuTimer(&CpuTimer0, 100, 1000000);
//ConfigCpuTimer(&CpuTimer1, 100, 1000000);
//ConfigCpuTimer(&CpuTimer2, 100, 1000000);
#endif
CpuTimer0Regs.PRD.all=7500;
CpuTimer0Regs.TPR.all=0;
CpuTimer0Regs.TIM.all=0;
CpuTimer0Regs.TPRH.all=0;
CpuTimer0Regs.TCR.bit.TSS=1;
CpuTimer0Regs.TCR.bit.SOFT=1;
CpuTimer0Regs.TCR.bit.FREE=1;
CpuTimer0Regs.TCR.bit.TRB=1;
CpuTimer0Regs.TCR.bit.TIE=1;
CpuTimer0.InterruptCount=0;
startCpuTimer0();
IER |= M_INT1;
//IER |= M_INT13;
//IER |= M_INT14;
// Enable TINT0 in the PIE: Group 1 interrupt 7
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
ADstart=0;
update =1;
flag=0;
flag1=2;
DutyFine =0;
DutyFine1 =0;
DutyFine2 =0;
swon=1;
MXI =0;
MXU=0;
// temp[6]=0;
Uref=1.5;
Ek_U=Ek1_U=Ek_I=Ek1_I=0;
U_Uk=0;
I_Uk=0;
UpU_max=2;
UpU_min=0;
PWM_max=3200;
PWM_min=0;
Kp_U=10;
Ki_U=5;
Kp_I=4000;
Ki_I=15;
PWM_count=900;
MXU_M=0;
MXI_M=0;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
// Some useful Period vs Frequency values
// SYSCLKOUT = 150MHz 100 MHz
// -----------------------------------------
// Period Frequency Frequency
// 1000 150 kHz 100 KHz
// 800 187 kHz 125 KHz
// 600 250 kHz 167 KHz
// 500 300 kHz 200 KHz
// 250 600 kHz 400 KHz
// 200 750 kHz 500 KHz
// 100 1.5 MHz 1.0 MHz
// 50 3.0 MHz 2.0 MHz
// 25 6.0 MHz 4.0 MHz
// 20 7.5 MHz 5.0 MHz
// 12 12.5 MHz 8.33 MHz
// 10 15.0 MHz 10.0 MHz
// 9 16.7 MHz 11.1 MHz
// 8 18.8 MHz 12.5 MHz
// 7 21.4 MHz 14.3 MHz
// 6 25.0 MHz 16.7 MHz
// 5 30.0 MHz 20.0 MHz
//====================================================================
// ePWM and HRPWM register initializaition
//====================================================================
// ePWM1 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz)
// HRPWM2_Config(3750); // ePWM2 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz)
//HRPWM3_Config(100); // ePWM3 target, 15 MHz PWM (SYSCLK=150MHz) or 10 MHz PWM (SYSCLK=100MHz)
HRPWM4_Config(4000); // ePWM4 target, 7.5 MHz PWM (SYSCLK=150MHz) or 5 MHz PWM (SYSCLK=100MHz)
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// IER |= M_INT8;
EINT;
while (1)
{
if(ADstart==1)
{
ADstart=0;
AD_convert();
// HF=MXI-41942;
// EPwm4Regs.CMPA.half.CMPA = HF;
PIDControl(MXU,MXI);
pwm_control(PWM_count);
}
EPwm1Regs.CMPA.half.CMPA = DutyFine;
}
}
void HRPWM1_Config(period)
{
// ePWM1 register configuration with HRPWM
// ePWM1A toggle low/high with MEP control on Rising edge
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
EPwm1Regs.TBPRD = period-1; // PWM frequency = 1 / period
EPwm1Regs.CMPA.half.CMPA =0; // set duty 50% initially
EPwm1Regs.CMPA.half.CMPAHR = 0;//(1 << 8); // initialize HRPWM extension
EPwm1Regs.CMPB = 0; // set duty 50% initially
EPwm1Regs.TBPHS.all = 0;
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE =TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPWM1 is the Master
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET ;
// EPwm1Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM1A on Zero
// EPwm1Regs.AQCTLB.bit.CAD = AQ_CLEAR;
// Active Low PWMs - Setup Deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;//DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = 400;//EPWM1_MIN_DB;
EPwm1Regs.DBFED = 400;//EPWM1_MIN_DB;
/*
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