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Clock Generator ad9516.pdf 1.82MB

14-Output Clock Generator with

Integrated 2.8 GHz VCO

AD9516-0

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Low phase noise, phase-locked loop

On-chip VCO tunes from 2.55 GHz to 2.95 GHz

External VCO/VCXO to 2.4 GHz optional

One differential or two single-ended reference inputs

Reference monitoring capability

Auto and manual reference switchover/holdover modes

Autorecover from holdover

Accepts references to 250 MHz

Programmable delays in path to PFD

Digital or analog lock detect, selectable

3 pairs of 1.6 GHz LVPECL outputs

Each pair shares 1 to 32 divider with coarse phase delay

Additive output jitter 225 f

rms

Channel-to-channel skew paired outputs <10 ps

2 pairs of 800 MHz LVDS clock outputs

Each pair shares two cascaded 1 to 32 dividers with coarse

phase delay

Additive output jitter 275 f

rms

Fine delay adjust (ΔT) on each LVDS output

Eight 250 MHz CMOS outputs (two per LVDS output)

Automatic synchronization of all outputs on power-up

Manual synchronization of outputs as needed

Serial control port

64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

ATE

GENERAL DESCRIPTION

The AD9516-0

provides a multi-output clock distribution

function with subpicosecond jitter performance, along with an on-

chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to

2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz

may be used.

The AD9516-0 emphasizes low jitter and phase noise to

maximize data converter performance, and can benefit other

applications with demanding phase noise and jitter requirements.

FUNCTIONAL BLOCK DIAGRAM

REFIN

REF1

REF2

CLK

SWITCHOVER

AND MONITOR

PLL

DIVIDER

AND MUXs

VCO

STATUS

MONITOR

LVPECL

LVDS/CMOS

SERIAL CONTROL PORT

AND

DIGITAL LOGIC

AD9516-0

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

DIV/Φ DIV/Φ

DIV/Φ

ΔT

06419-001

Figure 1.

The AD9516-0 features six LVPECL outputs (in three pairs);

four LVDS outputs (in two pairs); and eight CMOS outputs

(two per LVDS output). The LVPECL outputs operate to

1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS

outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide

ratio and coarse delay (or phase) to be set. The range of division

for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs

allow a range of divisions up to a maximum of 1024.

The AD9516-0 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated

by connecting the charge pump supply (VCP) to 5.5 V. A

separate LVPECL power supply can be from 2.375 V to 3.6 V.

The AD9516-0 is specified for operation over the industrial

range of −40°C to +85°C.

AD9516 is used throughout to refer to all the members of the AD9516

family. However, when AD9516-0 is used it is referring to that specific

member of the AD9516 family.

AD9516-0

Rev. 0 | Page 2 of 84

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Power Supply Requirements ....................................................... 4

PLL Characteristics ...................................................................... 4

Clock Inputs.................................................................................. 6

Clock Outputs............................................................................... 6

Timing Characteristics ................................................................ 7

Clock Output Additive Phase Noise (Distribution Only; VCO

Divider Not Used) ........................................................................ 8

Clock Output Absolute Phase Noise (Internal VCO Used).... 9

Clock Output Absolute Time Jitter (Clock Generation Using

Internal VCO) ............................................................................. 10

Clock Output Absolute Time Jitter (Clock Cleanup Using

Internal VCO) ............................................................................. 10

Clock Output Absolute Time Jitter (Clock Generation Using

External VCXO) ......................................................................... 10

Clock Output Additive Time Jitter (VCO Divider Not Used)

....................................................................................................... 11

Clock Output Additive Time Jitter (VCO Divider Used) ..... 11

Delay Block Additive Time Jitter.............................................. 12

Serial Control Port ..................................................................... 12

SYNC

, and

RESET

Pins ..................................................... 13

LD, STATUS, REFMON Pins.................................................... 13

Power Dissipation....................................................................... 14

Timing Diagrams............................................................................ 15

Absolute Maximum Ratings.......................................................... 16

Thermal Resistance .................................................................... 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 19

Ter mi nol og y .................................................................................... 25

Detailed Block Diagram ................................................................ 26

Theory of Operation ...................................................................... 27

Operational Configurations...................................................... 27

High Frequency Clock Distribution—CLK or External

VCO >1600 MHz ................................................................... 27

Internal VCO and Clock Distribution................................. 29

Clock Distribution or External VCO <1600 MHz ............ 31

Phase-Locked Loop (PLL) .................................................... 33

Configuration of the PLL ...................................................... 33

Phase Frequency Detector (PFD) ........................................ 33

Charge Pump (CP)................................................................. 34

On-Chip VCO ........................................................................ 34

PLL External Loop Filter....................................................... 34

PLL Reference Inputs............................................................. 34

Reference Switchover............................................................. 35

Reference Divider R............................................................... 35

VCXO/VCO Feedback Divider N: P, A, B, R ..................... 35

Digital Lock Detect (DLD) ....................................................... 37

Analog Lock Detect (ALD)................................................... 37

Current Source Digital Lock Detect (DLD) ....................... 37

External VCXO/VCO Clock Input (CLK/

CLK

)................ 37

Holdover.................................................................................. 38

Manual Holdover Mode ........................................................ 38

Automatic/Internal Holdover Mode.................................... 38

Frequency Status Monitors ................................................... 39

VCO Calibration .................................................................... 40

Clock Distribution ..................................................................... 41

Internal VCO or External CLK as Clock Source ............... 41

CLK or VCO Direct to LVPECL Outputs........................... 41

Clock Frequency Division..................................................... 42

VCO Divider........................................................................... 42

Channel Dividers—LVPECL Outputs................................. 42

Channel Dividers—LVDS/CMOS Outputs........................ 44

Synchronizing the Outputs—SYNC Function ................... 47

Clock Outputs......................................................................... 49

LVPECL Outputs: OUT0 to OUT5 ..................................... 49

LVDS/CMOS Outputs: OUT6 to OUT9............................. 50

Reset Modes ................................................................................ 50

Power-On Reset—Start-Up Conditions when

Is Applied ........................................................................... 50

Asynchronous Reset via the

RESET

Pin ............................. 50

Soft Reset via 0x00<5> .......................................................... 50

Power-Down Modes .................................................................. 50

Chip Power-Down via

.................................................... 50

PLL Power-Down................................................................... 51

Distribution Power-Down .................................................... 51

AD9516-0

Rev. 0 | Page 3 of 84

Individual Clock Output Power-Down................................51

Individual Circuit Block Power-Down ................................51

Serial Control Port ..........................................................................52

Serial Control Port Pin Descriptions........................................52

General Operation of Serial Control Port ...............................52

Communication Cycle—Instruction Plus Data..................52

Write .........................................................................................52

Read ..........................................................................................53

The Instruction Word (16 Bits).................................................53

MSB/LSB First Transfers ............................................................53

Application Notes............................................................................79

Using the AD9516 Outputs for ADC Clock Applications ....79

LVPECL Clock Distribution ......................................................79

LVDS Clock Distribution...........................................................79

CMOS Clock Distribution.........................................................80

Outline Dimensions........................................................................81

Ordering Guide ...........................................................................81

REVISION HISTORY

4/07—Revision 0: Initial Version

AD9516-0

Rev. 0 | Page 4 of 84

SPECIFICATIONS

Typical (typ) is given for V

= V

S_LVPECL

= 3.3 V ± 5%; V

≤ V

≤ 5.25 V; T

= 25°C; R

SET

= 4.12 kΩ; CP

RSET

= 5.1 kΩ,

unless otherwise noted. Minimum (min) and maximum (max) values are given over full V

and T

(−40°C to +85°C) variation.

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

3.135 3.3 3.465 V This is 3.3 V ± 5%

S_LVPECL

2.375 V

V This is nominally 2.5 V to 3.3 V ± 5%

5.25 V This is nominally 3.3 V to 5.0 V ± 5%

RSET Pin Resistor 4.12 kΩ Sets internal biasing currents; connect to ground

CPRSET Pin Resistor 5.1 kΩ

Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);

actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground

BYPASS Pin Capacitor 220 nF Bypass for internal LDO regulator; necessary for LDO stability; connect to ground

PLL CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

VCO (ON-CHIP)

Frequency Range 2550 2950 MHz See Figure 15

VCO Gain (K

VCO

) 50 MHz/V See Figure 10

Tuning Voltage (V

) 0.5 V

− 0.5 V

≤ V

when using internal VCO; outside of this

range, the CP spurs may increase due to CP up/

down mismatch

Frequency Pushing (Open-Loop) 1 MHz/V

Phase Noise @ 100 kHz Offset −105 dBc/Hz f = 2800 MHz

Phase Noise @ 1 MHz Offset −123 dBc/Hz f = 2800 MHz

REFERENCE INPUTS

Differential Mode (REFIN, REFIN)

Differential mode (can accommodate single-

ended input by ac grounding undriven input)

Input Frequency 0 250 MHz

Frequencies below about 1 MHz should be

dc-coupled; be careful to match V

(self-bias voltage)

Input Sensitivity 250 mV p-p

PLL figure of merit will increase with increasing

slew rate; see

Figure 14

Self-Bias Voltage, REFIN 1.35 1.60 1.75 V Self-bias voltage of REFIN

Self-Bias Voltage, REFIN

1.30 1.50 1.60 V

Self-bias voltage of

REFIN

Input Resistance, REFIN 4.0 4.8 5.9 kΩ Self-biased

Input Resistance, REFIN

4.4 5.3 6.4 kΩ Self-biased

Dual Single-Ended Mode (REF1, REF2) Two single-ended CMOS-compatible inputs

Input Frequency (AC-Coupled) 20 250 MHz Slew rate > 50 V/μs

Input Frequency (DC-Coupled) 0 250 MHz Slew rate > 50 V/μs; CMOS levels

Input Sensitivity (AC-Coupled) 0.8 V p-p Should not exceed V

p-p

Input Logic High 2.0 V

Input Logic Low 0.8 V

Input Current −100 +100 μA

Input Capacitance 2 pF

Each pin, REFIN/

REFIN (REF1/REF2)

AD9516-0

Rev. 0 | Page 5 of 84

Parameter Min Typ Max Unit Test Conditions/Comments

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns, 2.9 ns

45 MHz Antibacklash pulse width = 6.0 ns

Antibacklash Pulse Width 1.3 ns 0x17<1:0> = 01b

2.9 ns 0x17<1:0> = 00b; 0x17<1:0> = 11b

6.0 ns 0x17<1:0> = 10b

CHARGE PUMP (CP)

Sink/Source Programmable

High Value 4.8 mA With CP

RSET

= 5.1 kΩ

Low Value 0.60 mA

Absolute Accuracy 2.5 % CP

= V

RSET

Range 2.7/10 kΩ

High Impedance Mode Leakage 1 nA

Sink-and-Source Current Matching 2 % 0.5 < CP

< V

− 0.5 V

vs. CP

1.5 % 0.5 < CP

< V

− 0.5 V

vs. Temperature 2 % CP

= V

/2 V

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 1 FD 300 MHz

P = 2 FD 600 MHz

P = 3 FD 900 MHz

P = 2 DM (2/3) 600 MHz

P = 4 DM (4/5) 1000 MHz

P = 8 DM (8/9) 2400 MHz

P = 16 DM (16/17) 3000 MHz

P = 32 DM (32/33) 3000 MHz

Prescaler Output Frequency 300 MHz

A, B counter input frequency (prescaler

input frequency divided by P)

PLL DIVIDER DELAYS Register 0x19: R <5:3>, N <2:0>; see Table 53

000 Off ps

001 330 ps

010 440 ps

011 550 ps

100 660 ps

101 770 ps

110 880 ps

111 990 ps

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge

Pump/Phase Frequency Detector

(In-Band Means Within the LBW

of the PLL)

The PLL in-band phase noise floor is estimated

by measuring the in-band phase noise at the

output of the VCO and subtracting 20log(N)

(where N is the value of the N divider)

@ 500 kHz PFD Frequency −165 dBc/Hz

@ 1 MHz PFD Frequency −162 dBc/Hz

@ 10 MHz PFD Frequency −151 dBc/Hz

@ 50 MHz PFD Frequency −143 dBc/Hz

PLL Figure of Merit (FOM) −220 dBc/Hz

Reference slew rate > 0.25 V/ns. FOM +10log (f

PFD

)

is an approximation of the PFD/CP in-band

phase noise (in the flat region) inside the PLL

loop bandwidth. When running closed loop,

the phase noise, as observed at the VCO output,

is increased by 20log(N)

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