module VGA_TEST(CLK,MD,VGA_HS,VGA_VS,R,G,B);
input CLK;
input MD; //the chioce of color
output VGA_HS; //shuiping shaomiao xinhao
output VGA_VS; //chuizhi shaomian xinhao
output R,G,B; //three colors
reg VGA_HS,VGA_VS;
reg clk_25;
reg[1:0] MMD;
reg[10:0] CC;
reg[10:0] LL;
reg[3:1] GRBX,GRBY,GRBP;
wire[3:1] GRB;
assign GRB[1]=(GRBP[1]^MD)&VGA_HS&VGA_VS;
assign GRB[2]=(GRBP[2]^MD)&VGA_HS&VGA_VS;
assign GRB[3]=(GRBP[3]^MD)&VGA_HS&VGA_VS;
always @(posedge MD)
begin
if(MD) begin
if(MMD==2'b10) MMD<=2'b00;
else MMD<=MMD+1'b1;
end
end
always @(MMD or GRBP or GRBY)
begin
if(MMD==2'b00) GRBP<=GRBX;
else if(MMD==2'b01) GRBP<=GRBY;
else if(MMD==2'b10) GRBP<=(GRBX^GRBY);
else GRBP<=3'b000;
end
always @(posedge CLK)
begin
clk_25=~clk_25;//VGA_CLK 25MHZ
end
/*chansheng chang tongbu xinhao*/
always @(posedge clk_25 or negedge MD)
begin
if(!MD)
begin
CC<=0;
VGA_HS<=1'b1;
end
else
begin
if(CC<'d800) //VGA_HS=800*VGA_CLK
CC<=CC+1'b1;
else
CC<=0;
if(CC=='d16)
VGA_HS<=1'b0;
if(CC=='d96+'d16)
VGA_HS<=1'b1;
end
end
always @(posedge VGA_HS or negedge MD)
begin
if(!MD)
begin
LL<=0;
VGA_VS<=1'b1;
end
else
begin
if(LL<'d525) //VGA_VS=525*VGA_CLK
LL<=LL+1'b1;
else
LL<=0;
if(LL=='d10)
VGA_VS<=1'b0;
if(LL=='d2+'d10)
VGA_VS<=1'b1;
end
end
always @(CC or LL)
begin
/*chansheng caise shutiao*/
if(CC<'d240) GRBX<=3'b111;
else if(CC<'d320) GRBX<=3'b110;
else if(CC<'d400) GRBX<=3'b101;
else if(CC<'d480) GRBX<=3'b100;
else if(CC<'d560) GRBX<=3'b011;
else if(CC<'d640) GRBX<=3'b010;
else if(CC<'d720) GRBX<=3'b001;
else GRBX<=3'b000;
/*chansheng caise hengtiao*/
if(LL<'d240) GRBY<=3'b111;
else if(LL<'d320) GRBY<=3'b110;
else if(LL<'d400) GRBY<=3'b101;
else if(LL<'d480) GRBY<=3'b100;
else if(LL<'d560) GRBY<=3'b011;
else if(LL<'d640) GRBY<=3'b010;
else if(LL<'d720) GRBY<=3'b001;
else GRBY<=3'b000;
end
assign R=GRB[2];
assign G=GRB[3];
assign B=GRB[1];
endmodule
