lfsr.v
Fri Jan 12 22:45:52 2018
Page 1
1 `timescale 1ns / 1ps
2 //////////////////////////////////////////////////////////////////////////////////
3 // Company:
4 // Engineer:
5 //
6 // Create Date: 14:06:39 01/12/2018
7 // Design Name:
8 // Module Name: lfsr
9 // Project Name:
10 // Target Devices:
11 // Tool versions:
12 // Description:
13 //
14 // Dependencies:
15 //
16 // Revision:
17 // Revision 0.01 - File Created
18 // Additional Comments:
19 //
20 //////////////////////////////////////////////////////////////////////////////////
21 module lfsr(clk,rst,lfsr,cnt);
22 input clk,rst;
23 output reg[4:0]lfsr;
24 output reg[4:0]cnt;
25 always@(posedge clk)
26 begin
27 if(lfsr==5'b11111)
28 cnt<=1'd1;
29 else
30 cnt<=cnt+1'd1;
31 end
32
33 reg[20:0]clk_sig;
34 reg clk_1;
35 initial
36 clk_sig=4'b0000;
37 always@(posedge clk)
38 begin
39 clk_sig=clk_sig+1;
40 clk_1=clk_sig[16];
41 end
42
43 always@(posedge clk_1 or negedge rst)
44 begin
45 if(rst==0)
46 lfsr<=5'b11111;
47 else
48 begin
49 lfsr[0]<=lfsr[1];
50 lfsr[1]<=lfsr[2];
51 lfsr[2]<=lfsr[3];
52 lfsr[3]<=lfsr[4]^lfsr[0];
53 lfsr[4]<=lfsr[0];
54 end
55 end
56
57 endmodule
58
59 //testbench
60 module lfsr_tb;
61 reg clk_tb;