/**********************************************************
* Copyright 2008-2009 VMware, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
**********************************************************/
#include "pipe/p_shader_tokens.h"
#include "tgsi/tgsi_dump.h"
#include "tgsi/tgsi_parse.h"
#include "util/u_memory.h"
#include "util/u_math.h"
#include "svga_tgsi_emit.h"
#include "svga_context.h"
static boolean emit_vs_postamble( struct svga_shader_emitter *emit );
static boolean emit_ps_postamble( struct svga_shader_emitter *emit );
static unsigned
translate_opcode(
uint opcode )
{
switch (opcode) {
case TGSI_OPCODE_ABS: return SVGA3DOP_ABS;
case TGSI_OPCODE_ADD: return SVGA3DOP_ADD;
case TGSI_OPCODE_BREAKC: return SVGA3DOP_BREAKC;
case TGSI_OPCODE_DP2A: return SVGA3DOP_DP2ADD;
case TGSI_OPCODE_DP3: return SVGA3DOP_DP3;
case TGSI_OPCODE_DP4: return SVGA3DOP_DP4;
case TGSI_OPCODE_FRC: return SVGA3DOP_FRC;
case TGSI_OPCODE_MAD: return SVGA3DOP_MAD;
case TGSI_OPCODE_MAX: return SVGA3DOP_MAX;
case TGSI_OPCODE_MIN: return SVGA3DOP_MIN;
case TGSI_OPCODE_MOV: return SVGA3DOP_MOV;
case TGSI_OPCODE_MUL: return SVGA3DOP_MUL;
case TGSI_OPCODE_NOP: return SVGA3DOP_NOP;
case TGSI_OPCODE_NRM4: return SVGA3DOP_NRM;
default:
debug_printf("Unkown opcode %u\n", opcode);
assert( 0 );
return SVGA3DOP_LAST_INST;
}
}
static unsigned translate_file( unsigned file )
{
switch (file) {
case TGSI_FILE_TEMPORARY: return SVGA3DREG_TEMP;
case TGSI_FILE_INPUT: return SVGA3DREG_INPUT;
case TGSI_FILE_OUTPUT: return SVGA3DREG_OUTPUT; /* VS3.0+ only */
case TGSI_FILE_IMMEDIATE: return SVGA3DREG_CONST;
case TGSI_FILE_CONSTANT: return SVGA3DREG_CONST;
case TGSI_FILE_SAMPLER: return SVGA3DREG_SAMPLER;
case TGSI_FILE_ADDRESS: return SVGA3DREG_ADDR;
default:
assert( 0 );
return SVGA3DREG_TEMP;
}
}
static SVGA3dShaderDestToken
translate_dst_register( struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn,
unsigned idx )
{
const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
SVGA3dShaderDestToken dest;
switch (reg->Register.File) {
case TGSI_FILE_OUTPUT:
/* Output registers encode semantic information in their name.
* Need to lookup a table built at decl time:
*/
dest = emit->output_map[reg->Register.Index];
break;
default:
{
unsigned index = reg->Register.Index;
assert(index < SVGA3D_TEMPREG_MAX);
index = MIN2(index, SVGA3D_TEMPREG_MAX - 1);
dest = dst_register(translate_file(reg->Register.File), index);
}
break;
}
dest.mask = reg->Register.WriteMask;
assert(dest.mask);
if (insn->Instruction.Saturate)
dest.dstMod = SVGA3DDSTMOD_SATURATE;
return dest;
}
static struct src_register
swizzle( struct src_register src,
int x,
int y,
int z,
int w )
{
x = (src.base.swizzle >> (x * 2)) & 0x3;
y = (src.base.swizzle >> (y * 2)) & 0x3;
z = (src.base.swizzle >> (z * 2)) & 0x3;
w = (src.base.swizzle >> (w * 2)) & 0x3;
src.base.swizzle = TRANSLATE_SWIZZLE(x,y,z,w);
return src;
}
static struct src_register
scalar( struct src_register src,
int comp )
{
return swizzle( src, comp, comp, comp, comp );
}
static INLINE boolean
svga_arl_needs_adjustment( const struct svga_shader_emitter *emit )
{
int i;
for (i = 0; i < emit->num_arl_consts; ++i) {
if (emit->arl_consts[i].arl_num == emit->current_arl)
return TRUE;
}
return FALSE;
}
static INLINE int
svga_arl_adjustment( const struct svga_shader_emitter *emit )
{
int i;
for (i = 0; i < emit->num_arl_consts; ++i) {
if (emit->arl_consts[i].arl_num == emit->current_arl)
return emit->arl_consts[i].number;
}
return 0;
}
static struct src_register
translate_src_register( const struct svga_shader_emitter *emit,
const struct tgsi_full_src_register *reg )
{
struct src_register src;
switch (reg->Register.File) {
case TGSI_FILE_INPUT:
/* Input registers are referred to by their semantic name rather
* than by index. Use the mapping build up from the decls:
*/
src = emit->input_map[reg->Register.Index];
break;
case TGSI_FILE_IMMEDIATE:
/* Immediates are appended after TGSI constants in the D3D
* constant buffer.
*/
src = src_register( translate_file( reg->Register.File ),
reg->Register.Index + emit->imm_start );
break;
default:
src = src_register( translate_file( reg->Register.File ),
reg->Register.Index );
break;
}
/* Indirect addressing.
*/
if (reg->Register.Indirect) {
if (emit->unit == PIPE_SHADER_FRAGMENT) {
/* Pixel shaders have only loop registers for relative
* addressing into inputs. Ignore the redundant address
* register, the contents of aL should be in sync with it.
*/
if (reg->Register.File == TGSI_FILE_INPUT) {
src.base.relAddr = 1;
src.indirect = src_token(SVGA3DREG_LOOP, 0);
}
}
else {
/* Constant buffers only.
*/
if (reg->Register.File == TGSI_FILE_CONSTANT) {
/* we shift the offset towards the minimum */
if (svga_arl_needs_adjustment( emit )) {
src.base.num -= svga_arl_adjustment( emit );
}
src.base.relAddr = 1;
/* Not really sure what should go in the second token:
*/
src.indirect = src_token( SVGA3DREG_ADDR,
reg->Indirect.Index );
src.indirect.swizzle = SWIZZLE_XXXX;
}
}
}
src = swizzle( src,
reg->Register.SwizzleX,
reg->Register.SwizzleY,
reg->Register.SwizzleZ,
reg->Register.SwizzleW );
/* src.mod isn't a bitfield, unfortunately:
* See tgsi_util_get_full_src_register_sign_mode for implementation details.
*/
if (reg->Register.Absolute) {
if (reg->Register.Negate)
src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
else
src.base.srcMod = SVGA3DSRCMOD_ABS;
}
else {
if (reg->Register.Negate)
src.base.srcMod = SVGA3DSRCMOD_NEG;
else
src.base.srcMod = SVGA3DSRCMOD_NONE;
}
return src;
}
/*
* Get a temporary register.
* Note: if we exceed the temporary register limit we just use
* register SVGA3D_TEMPREG_MAX - 1.
*/
static INLINE SVGA3dShaderDestToken
get_temp( struct svga_shader_emitter *emit )
{
int i = emit->nr_hw_temp + emit->internal_temp
