vgic.rar_The Courtesy

/* * Copyright (C) 2012 ARM Ltd. * Author: Marc Zyngier <[email protected]> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <linux/cpu.h> #include <linux/kvm.h> #include <linux/kvm_host.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/uaccess.h> #include <linux/irqchip/arm-gic.h> #include <asm/kvm_emulate.h> #include <asm/kvm_arm.h> #include <asm/kvm_mmu.h> /* * How the whole thing works (courtesy of Christoffer Dall): * * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if * something is pending on the CPU interface. * - Interrupts that are pending on the distributor are stored on the * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land * ioctls and guest mmio ops, and other in-kernel peripherals such as the * arch. timers). * - Every time the bitmap changes, the irq_pending_on_cpu oracle is * recalculated * - To calculate the oracle, we need info for each cpu from * compute_pending_for_cpu, which considers: * - PPI: dist->irq_pending & dist->irq_enable * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn * registers, stored on each vcpu. We only keep one bit of * information per interrupt, making sure that only one vcpu can * accept the interrupt. * - If any of the above state changes, we must recalculate the oracle. * - The same is true when injecting an interrupt, except that we only * consider a single interrupt at a time. The irq_spi_cpu array * contains the target CPU for each SPI. * * The handling of level interrupts adds some extra complexity. We * need to track when the interrupt has been EOIed, so we can sample * the 'line' again. This is achieved as such: * * - When a level interrupt is moved onto a vcpu, the corresponding * bit in irq_queued is set. As long as this bit is set, the line * will be ignored for further interrupts. The interrupt is injected * into the vcpu with the GICH_LR_EOI bit set (generate a * maintenance interrupt on EOI). * - When the interrupt is EOIed, the maintenance interrupt fires, * and clears the corresponding bit in irq_queued. This allows the * interrupt line to be sampled again. * - Note that level-triggered interrupts can also be set to pending from * writes to GICD_ISPENDRn and lowering the external input line does not * cause the interrupt to become inactive in such a situation. * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become * inactive as long as the external input line is held high. */ #define VGIC_ADDR_UNDEF (-1) #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ #define IMPLEMENTER_ARM 0x43b #define GICC_ARCH_VERSION_V2 0x2 #define ACCESS_READ_VALUE (1 << 0) #define ACCESS_READ_RAZ (0 << 0) #define ACCESS_READ_MASK(x) ((x) & (1 << 0)) #define ACCESS_WRITE_IGNORED (0 << 1) #define ACCESS_WRITE_SETBIT (1 << 1) #define ACCESS_WRITE_CLEARBIT (2 << 1) #define ACCESS_WRITE_VALUE (3 << 1) #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1)) static int vgic_init(struct kvm *kvm); static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); static void vgic_update_state(struct kvm *kvm); static void vgic_kick_vcpus(struct kvm *kvm); static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi); static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg); static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc); static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr); static const struct vgic_ops *vgic_ops; static const struct vgic_params *vgic; /* * struct vgic_bitmap contains a bitmap made of unsigned longs, but * extracts u32s out of them. * * This does not work on 64-bit BE systems, because the bitmap access * will store two consecutive 32-bit words with the higher-addressed * register's bits at the lower index and the lower-addressed register's * bits at the higher index. * * Therefore, swizzle the register index when accessing the 32-bit word * registers to access the right register's value. */ #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64 #define REG_OFFSET_SWIZZLE 1 #else #define REG_OFFSET_SWIZZLE 0 #endif static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs) { int nr_longs; nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS); b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL); if (!b->private) return -ENOMEM; b->shared = b->private + nr_cpus; return 0; } static void vgic_free_bitmap(struct vgic_bitmap *b) { kfree(b->private); b->private = NULL; b->shared = NULL; } /* * Call this function to convert a u64 value to an unsigned long * bitmask * in a way that works on both 32-bit and 64-bit LE and BE platforms. * * Warning: Calling this function may modify *val. */ static unsigned long *u64_to_bitmask(u64 *val) { #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32 *val = (*val >> 32) | (*val << 32); #endif return (unsigned long *)val; } static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x, int cpuid, u32 offset) { offset >>= 2; if (!offset) return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE; else return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE); } static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x, int cpuid, int irq) { if (irq < VGIC_NR_PRIVATE_IRQS) return test_bit(irq, x->private + cpuid); return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared); } static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, int irq, int val) { unsigned long *reg; if (irq < VGIC_NR_PRIVATE_IRQS) { reg = x->private + cpuid; } else { reg = x->shared; irq -= VGIC_NR_PRIVATE_IRQS; } if (val) set_bit(irq, reg); else clear_bit(irq, reg); } static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) { return x->private + cpuid; } static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x) { return x->shared; } static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs) { int size; size = nr_cpus * VGIC_NR_PRIVATE_IRQS; size += nr_irqs - VGIC_NR_PRIVATE_IRQS; x->private = kzalloc(size, GFP_KERNEL); if (!x->private) return -ENOMEM; x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32); return 0; } static void vgic_free_bytemap(struct vgic_bytemap *b) { kfree(b->private); b->private = NULL; b->shared = NULL; } static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset) { u32 *reg; if (offset < VGIC_NR_PRIVATE_IRQS) { reg = x->private; offset += cpuid * VGIC_NR_PRIVATE_IRQS; } else { reg = x->shared; offset -= VGIC_NR_PRIVATE_IRQS; } return reg + (offset / sizeof(u32)); } #define VGIC_CFG_LEVEL 0 #define VGIC_CFG_EDGE 1 static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq) { struct vgic_dist *dist = &vcpu->kvm->arch.vgic; int irq_va