DRAM Memory
System: Lecture 10
Spring 2003
Bruce Jacob
David Wang
University of
Maryland
slide 1
Timing and Synchronization
Clk
SRC
DRAM Memory
System: Lecture 10
Spring 2003
Bruce Jacob
David Wang
University of
Maryland
slide 2
A Signaling System
Data In
Data out
(point A)
(point B)
V
ref
Transmission Line
1
2
3
4
5
Transmitter
Clocking mechanism
Receiver
Terminator
* Poulton ISSCC 1999 Signaling Tutorial
1. Transmitter: Encodes data as current/voltage level
2. Transmission Line: Deliver data from transmitter to
3. Receiver: Compare against reference to extract data
4. Terminator: Remove signal from line, once they’re
onto the line
receiver
received
5. Clock: Tells transmitter when to send, receiver when
to sample signal
DRAM Memory
System: Lecture 10
Spring 2003
Bruce Jacob
David Wang
University of
Maryland
slide 3
Global Clock I
D
Q
Clock
Data
D
Q
Transmitter Receiver
1
2
3
4
5
0
0
1
4
2
3
5
0: Assume data is stable for setup time before clock edge
1: Rising edge of transmitter clock
2: Transmitter begins to drive data
3: Signal reaches input of receiver.
4: Rising edge of receiver clock
5: Receiver latches data and drives internal signal lines
DRAM Memory
System: Lecture 10
Spring 2003
Bruce Jacob
David Wang
University of
Maryland
slide 4
Global Clock II
D
Q
Clock
Data
D
Q
Transmitter Receiver
1
2
3
4
5
0
0
1
4
2
3
5
- “Clock cycle” occurs between steps 1 and 4.
- Assume signal transported cleanly with one way wire
delay time between steps 2 and 3.
- If wire delay time exceeds cycle time, multiple bits
will be “in flight” simultaneously on the transmission
medium.
DRAM Memory
System: Lecture 10
Spring 2003
Bruce Jacob
David Wang
University of
Maryland
slide 5
Global Clock III - Parallel Data
D
Q
Data
D
Q
Transmitter
Receiver
2”
3”
5”
0”
0’ & 0“
1’ & 1”
2’ & 2”
3’ & 3”
D
Q
Clock
Data
D
Q
1’
2’
3’
4’
5’
0’
5’ & 5”
4”
1”
transmitter input
transmitter clock
transmitter output
receiver input
receiver output
4’ & 4”
receiver clock
- Skew and jitter eats into timing budget