BSIM4v4.8.0 Manual Copyright © 2013 UC Berkeley
BSIM4v4.8.0 MOSFET Model
-User’s Manual
Navid Paydavosi, Tanvir Hasan Morshed, Darsen D. Lu,
Wenwei (Morgan) Yang, Mohan V. Dunga, Xuemei (Jane) Xi, Jin He,
Weidong Liu, Kanyu, M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun Chan,
Ali M. Niknejad, Chenming Hu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA 94720
BSIM4v4.8.0 Manual Copyright © 2013 UC Berkeley
Developers:
BSIM4v4.8.0 Developers:
Professor Chenming Hu (project director), UC Berkeley
Professor Ali M. Niknejad (project director), UC Berkeley
Dr. Navid Paydavosi, UC Berkeley
Developers of BSIM4 Previous Versions:
Tanvir Morshed, UC Berkeley
Darsen Lu, UC Berkeley
Dr. Weidong Liu, Synopsys
Dr. Xiaodong Jin, Marvell
Dr. Kanyu (Mark) Cao, UC Berkeley
Dr. Jeff J. Ou, Intel
Dr. Jin He, UC Berkeley
Dr. Xuemei (Jane) Xi, UC Berkeley
Dr. Wenwei Yang
Dr. Mohan V. Dunga, UC Berkeley
Professor Ali M. Niknejad, UC Berkeley
Professor Chenming Hu, UC Berkeley
Web Sites:
BSIM4 web site with BSIM source code and documents:
http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4
Compact Model Coalition: http://www.si2.org/cmc_index.php
Technical Support:
http://www-device.eecs.berkeley.edu/bsim/contact.php
BSIM4v4.8.0 Manual Copyright © 2013 UC Berkeley
Acknowledgement:
The development of BSIM4.8.0 benefited from the input of many BSIM
users, especially the Compact Model Coalition (CMC) member companies.
The developers would like to thank Keith Green at TI, Jung-Suk Goo and
Wenwei Yang at Globalfoundries, Xingming Liu and Jushan Xie at Cadence,
Joddy Wang, Robin Tan, Jane Xi and Weidong Liu at Synopsys, Ben Gu at
Freescale, James Ma at ProPlus Design, Joe Watts at IBM, Geoffrey Coram
at Analog Device, Wei-hung Chen at UC Berkeley, for their valuable
assistance in identifying the desirable modifications and testing of the new
model.
The BSIM project is partially supported by SRC and CMC.
BSIM4v4.8.0 Manual Copyright © 2013 UC Berkeley
Contents
Chapter 1: Effective Oxide Thickness, Channel Length and Channel Width ................................... 1
1.1 Gate Dielectric Model ............................................................................................................ 3
1.2 Poly-Silicon Gate Depletion ................................................................................................... 4
Chapter 2: Threshold Voltage Model ............................................................................................ 10
2.1 Long-Channel Model With Uniform Doping ........................................................................ 10
2.2 Non-Uniform Vertical Doping .............................................................................................. 11
2.3 Non-Uniform Lateral Doping: Pocket (Halo) Implant .......................................................... 13
2.4 Short-Channel and DIBL Effects ........................................................................................... 14
2.5 Narrow-Width Effect ........................................................................................................... 17
Chapter 3: Channel Charge and Subthreshold Swing Models ....................................................... 20
3.1 Channel Charge Model ........................................................................................................ 20
3.2 Subthreshold Swing n .......................................................................................................... 23
Chapter 4: Gate Direct Tunneling Current Model ......................................................................... 25
4.1 Model Selectors ................................................................................................................... 26
4.2 Voltage Across Oxide V
ox
..................................................................................................... 26
4.3 Equations for Tunneling Currents........................................................................................ 27
4.3.1 Gate-to-Substrate Current (I
gb
= I
gbacc
+ I
gbinv
) ............................................................... 27
4.3.2 Gate-to-Channel Current (I
gc0
) and Gate-to-S/D (I
gs
and I
gd
) ......................................... 28
4.3.3. Partition of I
gc
.............................................................................................................. 29
Chapter 5: Drain Current Model .................................................................................................... 31
5.1 Bulk Charge Effect ............................................................................................................... 31
5.2 Unified Mobility Model ....................................................................................................... 31
5.3 Asymmetric and Bias-Dependent Source/ Drain Resistance Model ................................... 35
5.4 Drain Current for Triode Region .......................................................................................... 37
5.5 Velocity Saturation .............................................................................................................. 38
5.6 Saturation Voltage V
dsat
....................................................................................................... 38
5.6.1 Intrinsic case ................................................................................................................. 38
5.6.2 Extrinsic Case ................................................................................................................ 38
5.6.3V
dseff
Formulation ........................................................................................................... 39
5.7 Saturation-Region Output Conductance Model .................................................................. 39
BSIM4v4.8.0 Manual Copyright © 2013 UC Berkeley
5.7.1 Channel Length Modulation (CLM) .............................................................................. 41
5.7.2 Drain-Induced Barrier Lowering (DIBL)......................................................................... 42
5.7.3 Substrate Current Induced Body Effect (SCBE) ............................................................ 43
5.7.4 Drain-Induced Threshold Shift (DITS) by Pocket Implant ............................................ 44
5.8 Single-Equation Channel Current Model ............................................................................. 44
5.9 New Current Saturation Mechanisms: Velocity Overshoot and Source End Velocity Limit
Model ........................................................................................................................................ 45
5.9.1 Velocity Overshoot ....................................................................................................... 45
5.9.2 Source End Velocity Limit Model .................................................................................. 46
Chapter 6: Body Current Models ................................................................................................... 48
6.1 I
ii
Model ............................................................................................................................... 48
6.2 I
GIDL
and I
GISL
Model .............................................................................................................. 48
Chapter 7: Capacitance Model ...................................................................................................... 51
7.1 General Description ............................................................................................................. 51
7.2 Methodology for Intrinsic Capacitance Modeling ............................................................... 52
7.2.1 Basic Formulation ......................................................................................................... 52
7.2.2 Short Channel Model .................................................................................................... 54
7.2.3 Single Equation Formulation ........................................................................................ 56
7.2.4.Charge partitioning ....................................................................................................... 57
7.3 Charge-Thickness Capacitance Model (CTM) ...................................................................... 58
7.4 Intrinsic Capacitance Model Equations ............................................................................... 62
7.4.1 capMod = 0 ................................................................................................................... 62
7.4.2 capMod = 1 ................................................................................................................... 64
7.5 Fringing/Overlap Capacitance Models ................................................................................ 68
7.5.1 Fringing capacitance model .......................................................................................... 68
7.5.2 Overlap capacitance model .......................................................................................... 69
Chapter 8: New Material Models .................................................................................................. 72
8.1 Model Selector .................................................................................................................... 72
8.2 Non-Silicon Channel ............................................................................................................ 72
8.3 Non-SiO
2
Gate insulator ...................................................................................................... 73
8.4 Non-Poly Silicon Gate Dielectric .......................................................................................... 74
Chapter 9: High-Speed/RF Models ................................................................................................ 76