gcd.rar_ Verilog gcd_Verilog GCD_gcd_gcd verilog code_gcd_testbe
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2022-09-14
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gcd.rar （90个子文件） 
gcd src 
ucli.key 0B log 464B gcd_controller.v 2KB gcd_input_data 45B gcd_controller.v~ 2KB gcd_test_output 0B gcd_datapath.v~ 2KB DVEfiles session.tcl 8KB dve_gui.log 489B dve_history.log 215B gcd_top.v 1KB gcd_testbench.v 1KB simv 658KB gcd_top.v~ 1KB gcd_datapath.v 2KB simv.daidir topmodules 8B BzDP_1.tt 9KB heZTHe_1.db 920B .version 51B dve_macro.db 24B RRrKjd_1.db 2KB offfilename.db 72B modfilename.db 375B str.db 1003B didmap.db 146B external_functions 457B nCDh3c_1.db 3KB 2N5hNe_1.db 2KB AllModulesSkeletons.db 1KB 5NrI.tt 0B SmwM2c_1.db 1KB covg_defs 0B vcs_rebuild 975B mUldHc_1.db 984B 3CjfEb_1.db 5KB b9dpyc_1.db 3KB dve_filelist.db 166B vcs.key 19B gcd_testbench.v~ 1KB csrc BzDP_1_d.o 19KB 5NrIB_d.o 35KB 5NrI_d.o.incr 3KB BzDP_1_l.dat 103B BzDP_1_d.o.incr 478B vcspieces.incr 17B vcsconst.incr 2KB SIM_l.o 333B product_timestamp 0B idincr.db 12B filelist 225B Makefile 2KB vcstype.incr 645B 5NrI_d.o 3KB sim syn gcd_testbench-verilog-verilog.syn 300B EDFF-verilog.syn 282B log Mux3-verilog.pvl 2KB REDFF-verilog-verilog.syn 288B unmapped_db gcd_datapath-verilog.syn 289B MUX3.mr 23B Mux2-verilog-verilog.syn 290B EDFF.mr 23B GCD_TOP.mr 23B gcd_datapath-verilog.pvl 6KB command.log 171KB GCD_TESTBENCH.mr 23B gcd_controller-verilog.syn 294B gcd_top-verilog.pvl 4KB MUX2.mr 23B netlist GCD_CONTROLLER.mr 23B gcd_controller-verilog.pvl 6KB gcd_datapath-verilog-verilog.syn 297B .synopsys_dc.setup 1B mapped_db REDFF.mr 23B Mux2-verilog.pvl 2KB default.svf 0B EDFF-verilog-verilog.syn 290B EDFF-verilog.pvl 2KB gcd_controller-verilog-verilog.syn 302B Mux2-verilog.syn 282B gcd_testbench-verilog.syn 292B REDFF-verilog.syn 280B .vcsmx_rebuild 77B GCD_DATAPATH.mr 23B Mux3-verilog-verilog.syn 290B gcd_top-verilog-verilog.syn 288B REDFF-verilog.pvl 2KB script gcd_top-verilog.syn 280B gcd_testbench-verilog.pvl 5KB Mux3-verilog.syn 282B filenames.log 815B资源评论
