ADVANCE INFORMATION
1 OMAP-L137 Low-Power Applications Processor
1.1 Features
OMAP-L137 Low-Power Applications Processor
www.ti.com
SPRS563B – SEPTEMBER 2008 – REVISED DECEMBER 2008
– Six ALU (32-/40-Bit) Functional Units
• Applications
• Supports 32-Bit Integer, SP (IEEE Single
– Industrial Control
Precision/32-Bit) and DP (IEEE Double
– USB, Networking
Precision/64-Bit) Floating Point
– High-Speed Encoding
• Supports up to Four SP Additions Per
– Professional Audio
Clock, Four DP Additions Every 2
• Software Support
Clocks
– TI DSP/BIOS™
• Supports up to Two Floating Point (SP
or DP) Approximate Reciprocal or
– Chip Support Library and DSP Library
Square Root Operations Per Cycle
• Dual Core SoC
– Two Multiply Functional Units
– 300-MHz ARM926EJ-S™ RISC MPU
• Mixed-Precision IEEE Floating Point
– 300-MHz C674x VLIW DSP
Multiply Supported up to:
• ARM926EJ-S Core
– 2 SP x SP -> SP Per Clock
– 32-Bit and 16-Bit (Thumb®) Instructions
– 2 SP x SP -> DP Every Two Clocks
– DSP Instruction Extensions
– 2 SP x DP -> DP Every Three Clocks
– Single Cycle MAC
– 2 DP x DP -> DP Every Four Clocks
– ARM® Jazelle® Technology
• Fixed Point Multiply Supports Two 32 x
– EmbeddedICE-RT™ for Real-Time Debug
32-Bit Multiplies, Four 16 x 16-Bit
• ARM9 Memory Architecture
Multiplies, or Eight 8 x 8-Bit Multiplies
per Clock Cycle, and Complex Multiples
• C674x Instruction Set Features
– Instruction Packing Reduces Code Size
– Superset of the C67x+™ and C64x+™ ISAs
– All Instructions Conditional
– 2400/1800 C674x MIPS/MFLOPS
– Hardware Support for Modulo Loop
– Byte-Addressable (8-/16-/32-/64-Bit Data)
Operation
– 8-Bit Overflow Protection
– Protected Mode Operation
– Bit-Field Extract, Set, Clear
– Exceptions Support for Error Detection and
– Normalization, Saturation, Bit-Counting
Program Redirection
– Compact 16-Bit Instructions
• 128K-Byte RAM Shared Memory
• C674x Two Level Cache Memory Architecture
• 3.3V LVCMOS IOs (except for USB interfaces)
– 32K-Byte L1P Program RAM/Cache
• Two External Memory Interfaces:
– 32K-Byte L1D Data RAM/Cache
– EMIFA
– 256K-Byte L2 Unified Mapped RAM/Cache
• NOR (8-/16-Bit-Wide Data)
– Flexible RAM/Cache Partition (L1 and L2)
• NAND (8-/16-Bit-Wide Data)
– 1024K-Byte L2 ROM
• 16-Bit SDRAM With 128MB Address
• Enhanced Direct-Memory-Access Controller 3
Space
(EDMA3):
– EMIFB
– 2 Transfer Controllers
• 32-Bit or 16-Bit SDRAM With 256MB
– 32 Independent DMA Channels
Address Space
– 8 Quick DMA Channels
• Three Configurable 16550 type UART Modules:
– Programmable Transfer Burst Size
– UART0 With Modem Control Signals
• TMS320C674x Floating Point VLIW DSP Core
– 16-byte FIFO
– Load-Store Architecture With Non-Aligned
– 16x or 13x Oversampling Option
Support
• LCD Controller
– 64 General-Purpose Registers (32 Bit)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C6000, C6000 are trademarks of Texas Instruments.
ARM926EJ-S is a trademark of ARM Limited.
All other trademarks are the property of their respective owners.
ADVANCE INFORMATION concerns new products in the sampling
Copyright © 2008–2008, Texas Instruments Incorporated
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.