SDRAM.rar_tms320c5509a

#define CHIP_5509A #include <csl.h> #include <csl_emif.h> EMIF_Config emifCfg0 = { EMIF_EGCR_RMK( 1, //EMIF_EGCR_MEMFREQ_2X, EMIF_EGCR_WPE_OFF, EMIF_EGCR_MEMCEN_ON, EMIF_EGCR_NOHOLD_NOHOLD), EMIF_EMIRST_RMK( EMIF_EMIRST_EMIRST_0F( 0xFFFF )), /* CE0_1, CE0_2, & CE0_3 */ EMIF_CEx1_RMK( EMIF_CEx1_MTYPE_SDRAM32, EMIF_CEx1_RDSETUP_OF( 15), EMIF_CEx1_RDSTROBE_OF( 63), EMIF_CEx1_RDHOLD_OF( 3 )), EMIF_CEx2_RMK( EMIF_CEx2_RDEXHLD_OF( 1), EMIF_CEx2_WREXHLD_OF( 1), EMIF_CEx2_WRSETUP_OF( 15), EMIF_CEx2_WRSTROBE_OF( 63), EMIF_CEx2_WRHOLD_OF( 3 )), EMIF_CEx3_RMK( EMIF_CEx3_TIMOUT_OF( 0 ) ), /* CE1_1, CE1_2, & CE1_3 */ EMIF_CEx1_RMK( EMIF_CEx1_MTYPE_ASYNC16, EMIF_CEx1_RDSETUP_OF( 0), EMIF_CEx1_RDSTROBE_OF( 14), EMIF_CEx1_RDHOLD_OF( 0) ), EMIF_CEx2_RMK( EMIF_CEx2_RDEXHLD_OF( 0), EMIF_CEx2_WREXHLD_OF( 0), EMIF_CEx2_WRSETUP_OF( 0), EMIF_CEx2_WRSTROBE_OF( 14), EMIF_CEx2_WRHOLD_OF( 0 )), EMIF_CEx3_RMK( EMIF_CEx3_TIMOUT_OF( 100 )), /* CE2_1, CE2_2, & CE2_3 */ EMIF_CEx1_RMK( EMIF_CEx1_MTYPE_ASYNC16, EMIF_CEx1_RDSETUP_OF( 0), EMIF_CEx1_RDSTROBE_OF( 20), EMIF_CEx1_RDHOLD_OF( 0 ) ), EMIF_CEx2_RMK( EMIF_CEx2_RDEXHLD_OF( 0), EMIF_CEx2_WREXHLD_OF( 0), EMIF_CEx2_WRSETUP_OF( 0), EMIF_CEx2_WRSTROBE_OF( 20), EMIF_CEx2_WRHOLD_OF( 0 ) ), EMIF_CEx3_RMK( EMIF_CEx3_TIMOUT_OF( 100 ) ), /* CE3_1, CE3_2, & CE3_3 */ EMIF_CEx1_RMK( EMIF_CEx1_MTYPE_ASYNC16, EMIF_CEx1_RDSETUP_OF( 0), EMIF_CEx1_RDSTROBE_OF( 20), EMIF_CEx1_RDHOLD_OF( 0) ), EMIF_CEx2_RMK( EMIF_CEx2_RDEXHLD_OF( 0), EMIF_CEx2_WREXHLD_OF( 1), EMIF_CEx2_WRSETUP_OF( 1), EMIF_CEx2_WRSTROBE_OF( 20), EMIF_CEx2_WRHOLD_OF( 1) ), EMIF_CEx3_RMK( EMIF_CEx3_TIMOUT_OF( 100) ), /* SDRAM: SDC1, SDPER, INIT, & SDC2 */ EMIF_SDC1_MK( EMIF_SDC1_TRC_OF( 5), EMIF_SDC1_SDSIZE_16M, EMIF_SDC1_SDWID_OFF, EMIF_SDC1_RFEN_ENABLE, EMIF_SDC1_TRCD_OF( 1), EMIF_SDC1_TRP_OF( 1) ), EMIF_SDPER_RMK( EMIF_SDPER_PERIOD_OF( 0x578 ) ), EMIF_INIT_RMK( EMIF_SDINIT_INIT_OF( 0xFFFF) ), EMIF_SDC2_RMK( EMIF_SDC2_SDACC_16BITBUS, EMIF_SDC2_TMRD_OF( 1), EMIF_SDC2_TRAS_OF( 3), EMIF_SDC2_TACTV2ACTV_OF( 5 )) }; void SDRAM_init() { /* Initialize CSL */ CSL_init(); /* program EBSR 2 LSB bits */ asm(" AND #0xFFFD , port(#0x6C00) ; "); asm(" OR #0x0001 , port(#0x6C00) ; "); /* Configure EMIF */ EMIF_config(&emifCfg0); } int main() { SDRAM_init(); }