#ifndef __LMK04806__
#define __LMK04806__
/****************************************************************************
* MSB LSB
* Byte
* D26|D25||D24|.....D2|D1|D0|A4|A3|A2|A1|A0
* DATA[26:0] |Address[4:0]
* CPOL = 0; CPHA = 0
*****************************************************************************/
/*LMK04800 Register definition*/
//Register address definition
#define REG_ADDR(val) (val&0x1f)
//writable register
//R0
#define REG_ADDR_R0 0x0
#define CLKout_0_1_PD 0x1<<31
#define CLKout1_ADLY_SEL 0x1<<29
#define CLKout0_ADLY_SEL 0x1<<28
#define REG_R0_VAL CLKout_0_1_PD|CLKout0_1_DIV(25)|REG_ADDR(0)
//R1
#define REG_ADDR_R1 0x1
#define CLKout_2_3_PD 0x1<<31
#define CLKout3_ADLY_SEL 0x1<<29
#define CLKout2_ADLY_SEL 0x1<<28
#define CLKout2_3_DDLY(val) ((val&0x3ff)<<18)
#define POWERDOWN 0x1<<17
#define CLKout2_3_HS 0x1<<16
#define CLKout2_3_DIV(val) ((val&0x7ff)<<5)
#define REG_R1_VAL CLKout_2_3_PD|CLKout2_3_DIV(25)|REG_ADDR(1)
//R2
#define REG_ADDR_R2 0x2
#define CLKout_4_5_PD 0x1<<31
#define CLKout5_ADLY_SEL 0x1<<29
#define CLKout4_ADLY_SEL 0x1<<28
#define REG_R2_VAL CLKout_4_5_PD|CLKout4_5_DIV(25)|REG_ADDR(2)
//R3
#define REG_ADDR_R3 0x3
#define CLKout_6_7_PD 0x1<<31
#define CLKout6_7_OSCin_Sel 0x1<<30
#define CLKout7_ADLY_SEL 0x1<<29
#define CLKout6_ADLY_SEL 0x1<<28
#define REG_R3_VAL CLKout6_7_OSCin_Sel|CLKout6_7_DIV(1)|REG_ADDR(3)
//R4
#define REG_ADDR_R4 0x4
#define CLKout_8_9_PD 0x1<<31
#define CLKout8_9_OSCin_Sel 0x1<<30
#define CLKout9_ADLY_SEL 0x1<<29
#define CLKout8_ADLY_SEL 0x1<<28
#define REG_R4_VAL CLKout8_9_DIV(25)|REG_ADDR(4)
//R5
#define REG_ADDR_R5 0x5
#define CLKout10_11_PD 0x1<<31
#define CLKout11_ADLY_SEL 0x1<<29
#define CLKout10_ADLY_SEL 0x1<<28
#define REG_R5_VAL CLKout10_11_PD|CLKout6_7_OSCin_Sel|CLKout10_11_DIV(25)|REG_ADDR(5)
//R6
#define REG_ADDR_R6 0x6
#define CLKout3_TYPE(val) ((val&0xf)<<28)
#define CLKout2_TYPE(val) ((val&0xf)<<24)
#define CLKout1_TYPE(val) ((val&0xf)<<20)
#define REG_R6_VAL CLKout3_TYPE(0)|CLKout2_TYPE(0)|CLKout1_TYPE(0)|CLKout0_TYPE(0)|CLKout2_3_ADLY(0)|CLKout0_1_ADLY(0)|REG_ADDR(6)
//R7
#define REG_ADDR_R7 0x7
#define CLKout7_TYPE(val) ((val&0xf)<<28)
#define CLKout6_TYPE(val) ((val&0xf)<<24)
#define CLKout5_TYPE(val) ((val&0xf)<<20)
#define REG_R7_VAL CLKout7_TYPE(0)|CLKout6_TYPE(8)|CLKout5_TYPE(0)|CLKout4_TYPE(0)|CLKout6_7_ADLY(0)|CLKout4_5_ADLY(0)|REG_ADDR(7)
//R8
#define REG_ADDR_R8 0x8
#define CLKout11_TYPE(val) ((val&0xf)<<28)
#define CLKout10_TYPE(val) ((val&0xf)<<24)
#define REG_R8_VAL CLKout11_TYPE(0)|CLKout10_TYPE(0)|CLKout9_TYPE(0)|CLKout8_TYPE(1)|CLKout10_11_ADLY(0)|CLKout8_9_ADLY(0)|REG_ADDR(8)
//R10
#define REG_ADDR_R10 0xa
#define OSCout1_LVPECL_AMP(val) ((val&0x3)<<30)
#define R10_BIT_28 0x1<<28
#define OSCout0_TYPE(val) ((val&0xf)<<24)
#define EN_OSCout1 0x1<<23
#define EN_OSCout0 0x1<<22
#define REG_R10_VAL OSCout1_LVPECL_AMP(2)|R10_BIT_28|OSCout0_TYPE(1)|EN_OSCout0|OSCout_DIV(0)|R10_BIT_14|VCO_DIV(2)|FEEDBACK_MUX(0)|REG_ADDR(10)
//R11
#define REG_ADDR_R11 0xb
#define MODE(val) ((val&0x1f)<<27)
#define EN_SYNC 0x1<<26
#define NO_SYNC_CLKout10_11 0x1<<25
#define NO_SYNC_CLKout8_9 0x1<<24
#define NO_SYNC_CLKout6_7 0x1<<23
#define NO_SYNC_CLKout4_5 0x1<<22
#define NO_SYNC_CLKout2_3 0x1<<21
#define NO_SYNC_CLKout0_1 0x1<<20
#define REG_R11_VAL MODE(0)|EN_SYNC|NO_SYNC_CLKout8_9|NO_SYNC_CLKout6_7|SYNC_MUX(0)|SYNC_POL_INV|SYNC_TYPE(1)|REG_ADDR(11)
//R12
#define REG_ADDR_R12 0xc
#define LD_MUX(val) ((val&0x1f)<<27)
#define LD_TYPE(val) ((val&0x7)<<24)
#define REG_R12_VAL LD_MUX(3)|LD_TYPE(3)|R12_BITS_18_19|EN_TRACK|HOLDOVER_MODE(2)|R12_BITS_5|REG_ADDR(12)
//R31
#define REG_ADDR_R31 0x1f
//Sets the required state of the LEuWire pin when performing register readback.
#define READBACK_LE 0x1<<21
#define READBACK_ADDR(val) ((val&0x1f)<<16) //Register address
#define uWire_LOCK 0x1<<5 //Registers(R0-R30) locked, Write-protect
#define REG_R31_VAL READBACK_ADDR(31)|REG_ADDR(31)
//read only
//R12
//R23
//R31
#endif