--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Bin to Bcd converter
-- Input (data_in) width : 4
-- Output (data_out) width : 8
-- Enable (EN) active : high
--
-- Download from : http://www.pld.com.cn
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity bin2bcd is
port(
data_in : in std_logic_vector(3 downto 0);
EN : in std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity;
architecture bin2bcd of bin2bcd is
begin
process(data_in, EN)
variable data_in_TEMP : std_logic_vector(2 downto 0);
begin
data_in_TEMP := data_in(3 downto 1);
data_out <= (others => '0');
if EN='1' then
case data_in_TEMP is
when "000" => data_out(7 downto 1) <= "0000000";
when "001" => data_out(7 downto 1) <= "0000001";
when "010" => data_out(7 downto 1) <= "0000010";
when "011" => data_out(7 downto 1) <= "0000011";
when "100" => data_out(7 downto 1) <= "0000100";
when "101" => data_out(7 downto 1) <= "0001000";
when "110" => data_out(7 downto 1) <= "0001001";
when "111" => data_out(7 downto 1) <= "0001010";
when others => data_out <= (others => '0');
end case;
data_out(0) <= data_in(0);
end if;
end process;
end architecture;
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