ilsp.rar_V2 _ilsp

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP M68000 Hi-Performance Microprocessor Division M68060 Software Package Production Release P1.00 -- October 10, 1994 M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. THE SOFTWARE is provided on an "AS IS" basis and without warranty. To the maximum extent permitted by applicable law, MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE and any warranty against infringement with regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. To the maximum extent permitted by applicable law, IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE so long as this entire notice is retained without alteration in any modified and/or redistributed versions, and that such modified versions are clearly identified as such. No licenses are granted by implication, estoppel or otherwise under any patents or trademarks of Motorola, Inc. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # litop.s: # This file is appended to the top of the 060FPLSP package # and contains the entry points into the package. The user, in # effect, branches to one of the branch table entries located here. # bra.l _060LSP__idivs64_ short 0x0000 bra.l _060LSP__idivu64_ short 0x0000 bra.l _060LSP__imuls64_ short 0x0000 bra.l _060LSP__imulu64_ short 0x0000 bra.l _060LSP__cmp2_Ab_ short 0x0000 bra.l _060LSP__cmp2_Aw_ short 0x0000 bra.l _060LSP__cmp2_Al_ short 0x0000 bra.l _060LSP__cmp2_Db_ short 0x0000 bra.l _060LSP__cmp2_Dw_ short 0x0000 bra.l _060LSP__cmp2_Dl_ short 0x0000 # leave room for future possible aditions. align 0x200 ######################################################################### # XDEF **************************************************************** # # _060LSP__idivu64_(): Emulate 64-bit unsigned div instruction. # # _060LSP__idivs64_(): Emulate 64-bit signed div instruction. # # # # This is the library version which is accessed as a subroutine # # and therefore does not work exactly like the 680X0 div{s,u}.l # # 64-bit divide instruction. # # # # XREF **************************************************************** # # None. # # # # INPUT *************************************************************** # # 0x4(sp) = divisor # # 0x8(sp) = hi(dividend) # # 0xc(sp) = lo(dividend) # # 0x10(sp) = pointer to location to place quotient/remainder # # # # OUTPUT ************************************************************** # # 0x10(sp) = points to location of remainder/quotient. # # remainder is in first longword, quotient is in 2nd. # # # # ALGORITHM *********************************************************** # # If the operands are signed, make them unsigned and save the # # sign info for later. Separate out special cases like divide-by-zero # # or 32-bit divides if possible. Else, use a special math algorithm # # to calculate the result. # # Restore sign info if signed instruction. Set the condition # # codes before performing the final "rts". If the divisor was equal to # # zero, then perform a divide-by-zero using a 16-bit implemented # # divide instruction. This way, the operating system can record that # # the event occurred even though it may not point to the correct place. # # # ######################################################################### set POSNEG, -1 set NDIVISOR, -2 set NDIVIDEND, -3 set DDSECOND, -4 set DDNORMAL, -8 set DDQUOTIENT, -12 set DIV64_CC, -16 ########## # divs.l # ########## global _060LSP__idivs64_ _060LSP__idivs64_: # PROLOGUE BEGIN ######################################################## link.w %a6,&-16 movm.l &0x3f00,-(%sp) # save d2-d7 # fmovm.l &0x0,-(%sp) # save no fpregs # PROLOGUE END ########################################################## mov.w %cc,DIV64_CC(%a6) st POSNEG(%a6) # signed operation bra.b ldiv64_cont ########## # divu.l # ########## global _060LSP__idivu64_ _060LSP__idivu64_: # PROLOGUE BEGIN ######################################################## link.w %a6,&-16 movm.l &0x3f00,-(%sp) # save d2-d7 # fmovm.l &0x0,-(%sp) # save no fpregs # PROLOGUE END ########################################################## mov.w %cc,DIV64_CC(%a6) sf POSNEG(%a6) # unsigned operation ldiv64_cont: mov.l 0x8(%a6),%d7 # fetch divisor beq.w ldiv64eq0 # divisor is = 0!!! mov.l 0xc(%a6), %d5 # get dividend hi mov.l 0x10(%a6), %d6 # get dividend lo # separate signed and unsigned divide tst.b POSNEG(%a6) # signed or unsigned? beq.b ldspecialcases # use positive divide # save the sign of the divisor # make divisor unsigned if it's negative tst.l %d7 # chk sign of divisor slt NDIVISOR(%a6) # save sign of divisor bpl.b ldsgndividend neg.l %d7 # complement negative divisor # save the sign of the dividend # make dividend unsigned if it's negative ldsgndividend: tst.l %d5 # chk sign of hi(dividend) slt NDIVIDEND(%a6) # save sign of dividend bpl.b ldspecialcases mov.w &0x0, %cc # clear 'X' cc bit negx.l %d6 # complement signed dividend negx.l %d5 # extract some special cases: # - is (dividend == 0) ? # - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div) ldspecialcases: tst.l %d5 # is (hi(dividend) == 0) bne.b ldnormaldivide # no, so try it the long way tst.l %d6 # is (lo(dividend) == 0), too beq.w lddone # yes, so (dividend == 0) cmp.l %d7,%d6 # is (divisor <= lo(dividend)) bls.b ld32bitdivide # yes, so use 32 bit divide exg %d5,%d6 # q = 0, r = dividend bra.w ldivfinish # can't divide, we're done. ld32bitdivide: tdivu.l %d7, %d5:%d6 # it's only a 32/32 bit div! bra.b ldivfinish ldnormaldivide: # last special case: # - is hi(dividend) >= divisor ? if yes, then overflow cmp.l %d7,%d5 bls.b lddovf # answer won't fit in 32 bits # perform the divide algorithm: bsr.l ldclassical # do int divide # separate into signed and unsigned finishes. ldivfinish: tst.b POSNEG(%a6) # do divs, divu separately beq.b lddone # divu has no processing!!! # it was a divs.l, so ccode setting is a little more complicated... tst.b NDIVIDEND(%a6) # remainder has same sign beq.b ldcc # as dividend. neg.l %d5 # sgn(rem) = sgn(dividend) ldcc: mov.b NDIVISOR(%a6), %d0 eor.b %d0, NDIVIDEND(%a6) # chk if quotient is negative beq.b ldqpos # branch to quot positive # 0x80000000 is the largest number representable as a 32-bit negative # number. the negative of 0x80000000 is 0x80000000. cmpi.l %d6, &0x80000000 # will (-quot) fit in 32 bits? bhi.b lddovf neg.l %d6 # make (-quot) 2's comp bra.b lddone ldqpos: btst &0x1f, %d6 # will (+quot) fit in 32 bits? bne.b lddovf lddone: # if the register numbers are the same, only the quotient gets saved. # so, if we always save the quotient second, we save ourselves a cmp&beq andi.w &0x10,DIV64_CC(%a6) mov.w DIV64_CC(%a6),%cc tst.l %d6 # may set 'N' ccode bit # here, the result is in d1 and d0. the current strategy is to save # the values at the location pointed to by a0. # use movm here to not disturb the condition codes. ldexit: movm.l &0x0060,([0x14,%a6]) # save result # EPILOGUE BEGIN ######################################################## # fmovm.l (%sp)+,&0x0 # restore no fpregs movm.l (%sp)+,&0x00fc # restore d2-d7 unlk %a6 # EPILOGUE END ###