imx-pcm-dma.rar_SOC

/* * ARC700 VIPT Cache Management * * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs * -flush_cache_dup_mm (fork) * -likewise for flush_cache_mm (exit/execve) * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break) * * vineetg: Apr 2011 * -Now that MMU can support larger pg sz (16K), the determiniation of * aliasing shd not be based on assumption of 8k pg * * vineetg: Mar 2011 * -optimised version of flush_icache_range( ) for making I/D coherent * when vaddr is available (agnostic of num of aliases) * * vineetg: Mar 2011 * -Added documentation about I-cache aliasing on ARC700 and the way it * was handled up until MMU V2. * -Spotted a three year old bug when killing the 4 aliases, which needs * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03} * instead of paddr | {0x00, 0x01, 0x10, 0x11} * (Rajesh you owe me one now) * * vineetg: Dec 2010 * -Off-by-one error when computing num_of_lines to flush * This broke signal handling with bionic which uses synthetic sigret stub * * vineetg: Mar 2010 * -GCC can't generate ZOL for core cache flush loops. * Conv them into iterations based as opposed to while (start < end) types * * Vineetg: July 2009 * -In I-cache flush routine we used to chk for aliasing for every line INV. * Instead now we setup routines per cache geometry and invoke them * via function pointers. * * Vineetg: Jan 2009 * -Cache Line flush routines used to flush an extra line beyond end addr * because check was while (end >= start) instead of (end > start) * =Some call sites had to work around by doing -1, -4 etc to end param * =Some callers didnt care. This was spec bad in case of INV routines * which would discard valid data (cause of the horrible ext2 bug * in ARC IDE driver) * * vineetg: June 11th 2008: Fixed flush_icache_range( ) * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need * to be flushed, which it was not doing. * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API, * however ARC cache maintenance OPs require PHY addr. Thus need to do * vmalloc_to_phy. * -Also added optimisation there, that for range > PAGE SIZE we flush the * entire cache in one shot rather than line by line. For e.g. a module * with Code sz 600k, old code flushed 600k worth of cache (line-by-line), * while cache is only 16 or 32k. */ #include <linux/module.h> #include <linux/mm.h> #include <linux/sched.h> #include <linux/cache.h> #include <linux/mmu_context.h> #include <linux/syscalls.h> #include <linux/uaccess.h> #include <linux/pagemap.h> #include <asm/cacheflush.h> #include <asm/cachectl.h> #include <asm/setup.h> char *arc_cache_mumbojumbo(int c, char *buf, int len) { int n = 0; #define PR_CACHE(p, cfg, str) \ if (!(p)->ver) \ n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ else \ n += scnprintf(buf + n, len - n, \ str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ (p)->sz_k, (p)->assoc, (p)->line_len, \ (p)->vipt ? "VIPT" : "PIPT", \ (p)->alias ? " aliasing" : "", \ IS_ENABLED(cfg) ? "" : " (not used)"); PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); return buf; } /* * Read the Cache Build Confuration Registers, Decode them and save into * the cpuinfo structure for later use. * No Validation done here, simply read/convert the BCRs */ void read_decode_cache_bcr(void) { struct cpuinfo_arc_cache *p_ic, *p_dc; unsigned int cpu = smp_processor_id(); struct bcr_cache { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; #else unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; #endif } ibcr, dbcr; p_ic = &cpuinfo_arc700[cpu].icache; READ_BCR(ARC_REG_IC_BCR, ibcr); if (!ibcr.ver) goto dc_chk; BUG_ON(ibcr.config != 3); p_ic->assoc = 2; /* Fixed to 2w set assoc */ p_ic->line_len = 8 << ibcr.line_len; p_ic->sz_k = 1 << (ibcr.sz - 1); p_ic->ver = ibcr.ver; p_ic->vipt = 1; p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; dc_chk: p_dc = &cpuinfo_arc700[cpu].dcache; READ_BCR(ARC_REG_DC_BCR, dbcr); if (!dbcr.ver) return; BUG_ON(dbcr.config != 2); p_dc->assoc = 4; /* Fixed to 4w set assoc */ p_dc->line_len = 16 << dbcr.line_len; p_dc->sz_k = 1 << (dbcr.sz - 1); p_dc->ver = dbcr.ver; p_dc->vipt = 1; p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; } /* * 1. Validate the Cache Geomtery (compile time config matches hardware) * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn) * (aliasing D-cache configurations are not supported YET) * 3. Enable the Caches, setup default flush mode for D-Cache * 3. Calculate the SHMLBA used by user space */ void arc_cache_init(void) { unsigned int __maybe_unused cpu = smp_processor_id(); char str[256]; printk(arc_cache_mumbojumbo(0, str, sizeof(str))); if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; if (!ic->ver) panic("cache support enabled but non-existent cache\n"); if (ic->line_len != L1_CACHE_BYTES) panic("ICache line [%d] != kernel Config [%d]", ic->line_len, L1_CACHE_BYTES); if (ic->ver != CONFIG_ARC_MMU_VER) panic("Cache ver [%d] doesn't match MMU ver [%d]\n", ic->ver, CONFIG_ARC_MMU_VER); } if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; int handled; if (!dc->ver) panic("cache support enabled but non-existent cache\n"); if (dc->line_len != L1_CACHE_BYTES) panic("DCache line [%d] != kernel Config [%d]", dc->line_len, L1_CACHE_BYTES); /* check for D-Cache aliasing */ handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); if (dc->alias && !handled) panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); else if (!dc->alias && handled) panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n"); } } #define OP_INV 0x1 #define OP_FLUSH 0x2 #define OP_FLUSH_N_INV 0x3 #define OP_INV_IC 0x4 /* * Common Helper for Line Operations on {I,D}-Cache */ static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr, unsigned long sz, const int cacheop) { unsigned int aux_cmd, aux_tag; int num_lines; const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE; if (cacheop == OP_INV_IC) { aux_cmd = ARC_REG_IC_IVIL; #if (CONFIG_ARC_MMU_VER > 2) aux_tag = ARC_REG_IC_PTAG; #endif } else { /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; #if (CONFIG_ARC_MMU_VER > 2) aux_tag = ARC_REG_DC_PTAG; #endif } /* Ensure we properly floor/ceil the non-line aligned/sized requests * and have @paddr - aligned to cache line and integral @num_lines. * This however can be avoided for page sized since: * -@paddr will be cache-line aligned already (being page aligned) * -@sz will be integral multiple of line size (being page sized). */ if (!full_page_op) { sz += paddr & ~CACHE_LINE_MASK; paddr &= CACHE_LINE_MASK; vaddr &= CACHE_LINE_MASK; } num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); #if (CONFIG_ARC_MMU_VER <= 2) /* MMUv2 and before: paddr contains stuffed vaddrs bits */ paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; #else /* if V-P const for loop, PTAG can be written once outside loop */ if (full_page_op) write_aux_reg(aux_tag, paddr); #endif while (num_lines-- > 0) { #if (CONFIG_ARC_MMU_VER > 2) /* MMUv3, cache ops require paddr seperately */ if