组合逻辑电路设计
基本门电路用 vhdl 语言来描述十分方便。为方便起见，在下面的程序中，实现 9 种逻辑运
算、6 种移位运算以及高低双字节内容互换。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity luoji is
port(ctr : in bit_vector(3 downto 0);
a : in bit_vector(31 downto 0);
b : in bit_vector(31 downto 0);
y : out bit_vector(31 downto 0));
end;
architecture one of luoji is
signal temp: bit_vector(31 downto 0);
begin
process(ctr,a,b)
begin
case ctr is
when "0000"=>temp<=a and b;
when "0001"=>temp<=a or b;
when "0010"=>temp<=a nand b;
when "0011"=>temp<=a nor b;
when "0100"=>temp<=a xor b;
when "0101"=>temp<=not a xor b;
when "0110"=>temp<=a sll 1;
when "0111"=>temp<=a srl 1;
when "1000"=>temp<=a sla 1;
when "1001"=>temp<=a sra 1;
when "1010"=>temp<=a rol 1;
when "1011"=>temp<=a ror 1;
when "1100"=>temp<=not a;
when "1101"=>temp<=(not a(31 downto 16)) & a(15 downto 0);
when "1110"=>temp<=a(31 downto 16) &(not a(15 downto 0));
when "1111"=>temp<=a(15 downto 0) & a(31 downto 16);
when others=>null;
end case;
end process;
y<=temp ;
end;
