rtc-at91sam9.rar_AT91RM9200 RTC_Bronson

/* * "RTT as Real Time Clock" driver for AT91SAM9 SoC family * * (C) 2007 Michel Benoit * * Based on rtc-at91rm9200.c by Rick Bronson * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/time.h> #include <linux/rtc.h> #include <linux/interrupt.h> #include <linux/ioctl.h> #include <linux/slab.h> #include <linux/platform_data/atmel.h> #include <linux/io.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> #include <linux/clk.h> /* * This driver uses two configurable hardware resources that live in the * AT91SAM9 backup power domain (intended to be powered at all times) * to implement the Real Time Clock interfaces * * - A "Real-time Timer" (RTT) counts up in seconds from a base time. * We can't assign the counter value (CRTV) ... but we can reset it. * * - One of the "General Purpose Backup Registers" (GPBRs) holds the * base time, normally an offset from the beginning of the POSIX * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the * local timezone's offset. * * The RTC's value is the RTT counter plus that offset. The RTC's alarm * is likewise a base (ALMV) plus that offset. * * Not all RTTs will be used as RTCs; some systems have multiple RTTs to * choose from, or a "real" RTC module. All systems have multiple GPBR * registers available, likewise usable for more than "RTC" support. */ #define AT91_RTT_MR 0x00 /* Real-time Mode Register */ #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ #define AT91_RTT_VR 0x08 /* Real-time Value Register */ #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ #define AT91_RTT_SR 0x0c /* Real-time Status Register */ #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ /* * We store ALARM_DISABLED in ALMV to record that no alarm is set. * It's also the reset value for that field. */ #define ALARM_DISABLED ((u32)~0) struct sam9_rtc { void __iomem *rtt; struct rtc_device *rtcdev; u32 imr; struct regmap *gpbr; unsigned int gpbr_offset; int irq; struct clk *sclk; }; #define rtt_readl(rtc, field) \ readl((rtc)->rtt + AT91_RTT_ ## field) #define rtt_writel(rtc, field, val) \ writel((val), (rtc)->rtt + AT91_RTT_ ## field) static inline unsigned int gpbr_readl(struct sam9_rtc *rtc) { unsigned int val; regmap_read(rtc->gpbr, rtc->gpbr_offset, &val); return val; } static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val) { regmap_write(rtc->gpbr, rtc->gpbr_offset, val); } /* * Read current time and date in RTC */ static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm) { struct sam9_rtc *rtc = dev_get_drvdata(dev); u32 secs, secs2; u32 offset; /* read current time offset */ offset = gpbr_readl(rtc); if (offset == 0) return -EILSEQ; /* reread the counter to help sync the two clock domains */ secs = rtt_readl(rtc, VR); secs2 = rtt_readl(rtc, VR); if (secs != secs2) secs = rtt_readl(rtc, VR); rtc_time_to_tm(offset + secs, tm); dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readtime", 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); return 0; } /* * Set current time and date in RTC */ static int at91_rtc_settime(struct device *dev, struct rtc_time *tm) { struct sam9_rtc *rtc = dev_get_drvdata(dev); int err; u32 offset, alarm, mr; unsigned long secs; dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "settime", 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); err = rtc_tm_to_time(tm, &secs); if (err != 0) return err; mr = rtt_readl(rtc, MR); /* disable interrupts */ rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)); /* read current time offset */ offset = gpbr_readl(rtc); /* store the new base time in a battery backup register */ secs += 1; gpbr_writel(rtc, secs); /* adjust the alarm time for the new base */ alarm = rtt_readl(rtc, AR); if (alarm != ALARM_DISABLED) { if (offset > secs) { /* time jumped backwards, increase time until alarm */ alarm += (offset - secs); } else if ((alarm + offset) > secs) { /* time jumped forwards, decrease time until alarm */ alarm -= (secs - offset); } else { /* time jumped past the alarm, disable alarm */ alarm = ALARM_DISABLED; mr &= ~AT91_RTT_ALMIEN; } rtt_writel(rtc, AR, alarm); } /* reset the timer, and re-enable interrupts */ rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST); return 0; } static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) { struct sam9_rtc *rtc = dev_get_drvdata(dev); struct rtc_time *tm = &alrm->time; u32 alarm = rtt_readl(rtc, AR); u32 offset; offset = gpbr_readl(rtc); if (offset == 0) return -EILSEQ; memset(alrm, 0, sizeof(*alrm)); if (alarm != ALARM_DISABLED && offset != 0) { rtc_time_to_tm(offset + alarm, tm); dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readalarm", 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN) alrm->enabled = 1; } return 0; } static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) { struct sam9_rtc *rtc = dev_get_drvdata(dev); struct rtc_time *tm = &alrm->time; unsigned long secs; u32 offset; u32 mr; int err; err = rtc_tm_to_time(tm, &secs); if (err != 0) return err; offset = gpbr_readl(rtc); if (offset == 0) { /* time is not set */ return -EILSEQ; } mr = rtt_readl(rtc, MR); rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); /* alarm in the past? finish and leave disabled */ if (secs <= offset) { rtt_writel(rtc, AR, ALARM_DISABLED); return 0; } /* else set alarm and maybe enable it */ rtt_writel(rtc, AR, secs - offset); if (alrm->enabled) rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "setalarm", tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec); return 0; } static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) { struct sam9_rtc *rtc = dev_get_drvdata(dev); u32 mr = rtt_readl(rtc, MR); dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr); if (enabled) rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN); else rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN); return 0; } /* * Provide additional RTC information in /proc/driver/rtc */ static int at91_rtc_proc(struct device *dev, struct seq_file *seq) { struct sam9_rtc *rtc = dev_get_drvdata(dev); u32 mr = mr = rtt_readl(rtc, MR); seq_printf(seq, "update_IRQ\t: %s\n", (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no"); return 0; } /* * IRQ handler for the RTC */ static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc) { struct sam9_rtc *rtc = _rtc; u32 sr, mr; unsigned long events = 0; /* Shared interrupt may be for another device. Note: reading * SR clears it, so we must only read it in this irq handler! */ mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN); sr = rtt_readl(rtc, SR) & (mr >> 16); if (!sr) return IRQ_NONE; /* alarm status */ if (sr & AT91_RTT_ALMS) events |= (RTC_AF | RTC_IRQF); /* timer update/increment */ if (sr & AT91_RTT_RTTINC) events |= (RTC_UF | RTC_IRQF); rtc_update_irq(rtc->rtcdev,