gpio-pch.rar_The Store

#include <linux/module.h> #include <linux/kernel.h> #include <linux/pci.h> #include <linux/gpio.h> #include <linux/interrupt.h> #include <linux/irq.h> #define PCH_EDGE_FALLING 0 #define PCH_EDGE_RISING BIT(0) #define PCH_LEVEL_L BIT(1) #define PCH_LEVEL_H (BIT(0) | BIT(1)) #define PCH_EDGE_BOTH BIT(2) #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) #define PCH_IRQ_BASE 24 struct pch_regs { u32 ien; u32 istatus; u32 idisp; u32 iclr; u32 imask; u32 imaskclr; u32 po; u32 pi; u32 pm; u32 im0; u32 im1; u32 reserved[3]; u32 gpio_use_sel; u32 reset; }; enum pch_type_t { INTEL_EG20T_PCH, OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */ OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */ }; /* Specifies number of GPIO PINS */ static int gpio_pins[] = { [INTEL_EG20T_PCH] = 12, [OKISEMI_ML7223m_IOH] = 8, [OKISEMI_ML7223n_IOH] = 8, }; /** * struct pch_gpio_reg_data - The register store data. * @ien_reg: To store contents of IEN register. * @imask_reg: To store contents of IMASK register. * @po_reg: To store contents of PO register. * @pm_reg: To store contents of PM register. * @im0_reg: To store contents of IM0 register. * @im1_reg: To store contents of IM1 register. * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register. * (Only ML7223 Bus-n) */ struct pch_gpio_reg_data { u32 ien_reg; u32 imask_reg; u32 po_reg; u32 pm_reg; u32 im0_reg; u32 im1_reg; u32 gpio_use_sel_reg; }; /** * struct pch_gpio - GPIO private data structure. * @base: PCI base address of Memory mapped I/O register. * @reg: Memory mapped PCH GPIO register list. * @dev: Pointer to device structure. * @gpio: Data for GPIO infrastructure. * @pch_gpio_reg: Memory mapped Register data is saved here * when suspend. * @lock: Used for register access protection * @irq_base: Save base of IRQ number for interrupt * @ioh: IOH ID * @spinlock: Used for register access protection */ struct pch_gpio { void __iomem *base; struct pch_regs __iomem *reg; struct device *dev; struct gpio_chip gpio; struct pch_gpio_reg_data pch_gpio_reg; int irq_base; enum pch_type_t ioh; spinlock_t spinlock; }; static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) { u32 reg_val; struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); unsigned long flags; spin_lock_irqsave(&chip->spinlock, flags); reg_val = ioread32(&chip->reg->po); if (val) reg_val |= (1 << nr); else reg_val &= ~(1 << nr); iowrite32(reg_val, &chip->reg->po); spin_unlock_irqrestore(&chip->spinlock, flags); } static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr) { struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); return ioread32(&chip->reg->pi) & (1 << nr); } static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, int val) { struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); u32 pm; u32 reg_val; unsigned long flags; spin_lock_irqsave(&chip->spinlock, flags); pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); pm |= (1 << nr); iowrite32(pm, &chip->reg->pm); reg_val = ioread32(&chip->reg->po); if (val) reg_val |= (1 << nr); else reg_val &= ~(1 << nr); iowrite32(reg_val, &chip->reg->po); spin_unlock_irqrestore(&chip->spinlock, flags); return 0; } static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) { struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); u32 pm; unsigned long flags; spin_lock_irqsave(&chip->spinlock, flags); pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); pm &= ~(1 << nr); iowrite32(pm, &chip->reg->pm); spin_unlock_irqrestore(&chip->spinlock, flags); return 0; } /* * Save register configuration and disable interrupts. */ static void pch_gpio_save_reg_conf(struct pch_gpio *chip) { chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); if (chip->ioh == INTEL_EG20T_PCH) chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); if (chip->ioh == OKISEMI_ML7223n_IOH) chip->pch_gpio_reg.gpio_use_sel_reg =\ ioread32(&chip->reg->gpio_use_sel); } /* * This function restores the register configuration of the GPIO device. */ static void pch_gpio_restore_reg_conf(struct pch_gpio *chip) { iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); /* to store contents of PO register */ iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); /* to store contents of PM register */ iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); if (chip->ioh == INTEL_EG20T_PCH) iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); if (chip->ioh == OKISEMI_ML7223n_IOH) iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel); } static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset) { struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio); return chip->irq_base + offset; } static void pch_gpio_setup(struct pch_gpio *chip) { struct gpio_chip *gpio = &chip->gpio; gpio->label = dev_name(chip->dev); gpio->dev = chip->dev; gpio->owner = THIS_MODULE; gpio->direction_input = pch_gpio_direction_input; gpio->get = pch_gpio_get; gpio->direction_output = pch_gpio_direction_output; gpio->set = pch_gpio_set; gpio->dbg_show = NULL; gpio->base = -1; gpio->ngpio = gpio_pins[chip->ioh]; gpio->can_sleep = 0; gpio->to_irq = pch_gpio_to_irq; } static int pch_irq_type(struct irq_data *d, unsigned int type) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct pch_gpio *chip = gc->private; u32 im, im_pos, val; u32 __iomem *im_reg; unsigned long flags; int ch, irq = d->irq; ch = irq - chip->irq_base; if (irq <= chip->irq_base + 7) { im_reg = &chip->reg->im0; im_pos = ch; } else { im_reg = &chip->reg->im1; im_pos = ch - 8; } dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n", __func__, irq, type, ch, im_pos); spin_lock_irqsave(&chip->spinlock, flags); switch (type) { case IRQ_TYPE_EDGE_RISING: val = PCH_EDGE_RISING; break; case IRQ_TYPE_EDGE_FALLING: val = PCH_EDGE_FALLING; break; case IRQ_TYPE_EDGE_BOTH: val = PCH_EDGE_BOTH; break; case IRQ_TYPE_LEVEL_HIGH: val = PCH_LEVEL_H; break; case IRQ_TYPE_LEVEL_LOW: val = PCH_LEVEL_L; break; default: goto unlock; } /* Set interrupt mode */ im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4)); iowrite32(im | (val << (im_pos * 4)), im_reg); /* And the handler */ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) __irq_set_handler_locked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) __irq_set_handler_locked(d->irq, handle_edge_irq); unlock: spin_unlock_irqrestore(&chip->spinlock, flags); return 0; } static void pch_irq_unmask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct pch_gpio *chip = gc->private; iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr); } static void pch_irq_mask(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct pch_gpio *chip = gc->private; iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask); } static void pch_irq_ack(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct pch_gpio *chip = gc->private; iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr); } static irqreturn_t pch_gpio_handler(int irq, void *dev_id) { struct pch_gpio *chip = dev_id; u32 reg_val = ioread32(&chip->reg->istatus); int i, ret = IRQ_NONE; for (i = 0; i < gpio_pins[chip->ioh]; i++) { if (reg