library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tlc is
Port ( clk,reset : in std_logic;
r1,y1,g1 : out std_logic;
r2,y2,g2 : out std_logic);
end tlc;
architecture Behavioral of tlc is
signal cnt1 : std_logic_vector(2 downto 0):= "000";
signal cnt2 : std_logic_vector(1 downto 0):= "00";
type state_type is (s0,s1,s2,s3) ;
signal state : state_type;
signal xx:std_logic_vector(21 downto 0):="0000000000000000000000";
signal clk1:std_logic;
begin
process(clk,reset)
begin
if reset='1'then
xx<="0000000000000000000000";
elsif(clk'event and clk = '1')then
xx<=xx+"00000000000000000000001";
end if;
end process;
clk1<=xx(21);
process(clk1,reset)
begin
if(reset ='1')then
r1 <= '0';
y1 <= '0';
g1 <= '0';
r2 <= '0';
y2 <= '0';
g2 <= '0';
elsif(clk1'event and clk1 = '1')then
case state is
when s0 =>
r1 <= '1';
y1 <= '0';
g1 <= '0';
r2 <= '0';
y2 <= '0';
g2 <= '1';
cnt1 <= cnt1 + '1';
if(cnt1(2) = '1')then
state <= s1;
cnt1 <= "000";
end if;
when s1 =>
r1 <= '1';
y1 <= '0';
g1 <= '0';
r2 <= '0';
y2 <= '1';
g2 <= '0';
cnt2 <= cnt2+ '1';
if(cnt2(1) = '1')then
state <= s2;
cnt2 <= "00";
end if;
when s2 =>
r1 <= '0';
y1 <= '0';
g1 <= '1';
r2 <= '1';
y2 <= '0';
g2 <= '0';
cnt1 <= cnt1+ '1';
if(cnt1(2) = '1')then
state <= s3;
cnt1 <= "000";
end if;
when s3 =>
r1 <= '0';
y1 <= '1';
g1 <= '0';
r2 <= '1';
y2 <= '0';
g2 <= '0';
cnt2 <= cnt2+ '1';
if(cnt2(1) = '1')then
state <= s0;
cnt2 <= "00";
end if;
end case;
end if;
end process;
end Behavioral;