yinpin.rar_音频_音频发生器

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is Port ( clk : in std_logic; index : in std_logic_vector(3 downto 0); ledA : out std_logic; seg : out std_logic_vector(6 downto 0); spkout : out std_logic); end top; architecture Behavioral of top is signal code : std_logic_vector(2 downto 0); signal tonetmp : integer range 0 to 2000; component tone is Port ( index : in std_logic_vector(3 downto 0); code : out std_logic_vector(2 downto 0); tone_out : out integer range 0 to 2000); end component; component speaker is Port ( clk : in std_logic; tonein : in integer range 0 to 2000; spks : out std_logic); end component; begin U1: tone port map (index,code,tonetmp); U2: speaker port map (clk,tonetmp,spkout); ledA <= '1'; process (code) begin CASE code is -- 0123456 when "000" => seg <= "0000001"; when "001" => seg <= "0000010"; when "010" => seg <= "0000100"; when "011" => seg <= "0001000"; when "100" => seg <= "0010000"; when "101" => seg <= "0100000"; when "110" => seg <= "1000000"; when others => seg <= "1111111"; end case; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity speaker is Port ( clk : in std_logic:='0'; tonein : in integer range 0 to 2000:=0; spks : out std_logic:='0'); end speaker; architecture Behavioral of speaker is signal divclk,fullspks : std_logic:='0'; begin divideclk: process(clk) variable count : integer range 0 to 50:=0; begin divclk <= '0'; if count=50 then divclk <= '1' ; count := 0; elsif clk'event and clk='1' then count := count + 1; end if; end process; genspks: process(divclk,tonein) variable cnt : integer range 0 to 2000:=0; begin if divclk'event and divclk='1' then if cnt=2000 then cnt := tonein; fullspks <= '1'; else cnt := cnt + 1; fullspks <='0'; end if; end if; end process; delayspks: process(fullspks) variable count1 : std_logic:='0'; begin if fullspks'event and fullspks='1' then count1 := not count1; if count1='1' then spks <= '1'; else spks <= '0'; end if; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tone is Port ( index : in std_logic_vector(3 downto 0); code : out std_logic_vector(2 downto 0); tone_out : out integer range 0 to 2000); end tone; architecture Behavioral of tone is begin process (index) begin case index is when "0001" => tone_out <= 92; code <= "000"; when "0010" => tone_out <= 300; code <= "001"; when "0011" => tone_out <= 485; code <= "010"; when "0100" => tone_out <= 568; code <= "011"; when "0101" => tone_out <= 725; code <= "100"; when "0110" => tone_out <= 864; code <= "101"; when others => tone_out <=2000; code <= "111"; end case; end process; end Behavioral; 現村2� #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "c9" ; NET "index<0>" LOC = "l13" ; NET "index<1>" LOC = "l14" ; NET "index<2>" LOC = "h18" ; NET "index<3>" LOC = "n17" ; NET "ledA" LOC = "f9" ; NET "seg<0>" LOC = "f12" ; NET "seg<1>" LOC = "e12" ; NET "seg<2>" LOC = "e11" ; NET "seg<3>" LOC = "f11" ; NET "seg<4>" LOC = "c11" ; NET "seg<5>" LOC = "d11" ; NET "seg<6>" LOC = "e9" ; NET "spkout" LOC = "e8" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE