/*
* NXP LPC32XX NAND SLC driver
*
* Authors:
* Kevin Wells <[email protected]>
* Roland Stigge <[email protected]>
*
* Copyright © 2011 NXP Semiconductors
* Copyright © 2012 Roland Stigge
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_mtd.h>
#include <linux/of_gpio.h>
#include <linux/mtd/lpc32xx_slc.h>
#define LPC32XX_MODNAME "lpc32xx-nand"
/**********************************************************************
* SLC NAND controller register offsets
**********************************************************************/
#define SLC_DATA(x) (x + 0x000)
#define SLC_ADDR(x) (x + 0x004)
#define SLC_CMD(x) (x + 0x008)
#define SLC_STOP(x) (x + 0x00C)
#define SLC_CTRL(x) (x + 0x010)
#define SLC_CFG(x) (x + 0x014)
#define SLC_STAT(x) (x + 0x018)
#define SLC_INT_STAT(x) (x + 0x01C)
#define SLC_IEN(x) (x + 0x020)
#define SLC_ISR(x) (x + 0x024)
#define SLC_ICR(x) (x + 0x028)
#define SLC_TAC(x) (x + 0x02C)
#define SLC_TC(x) (x + 0x030)
#define SLC_ECC(x) (x + 0x034)
#define SLC_DMA_DATA(x) (x + 0x038)
/**********************************************************************
* slc_ctrl register definitions
**********************************************************************/
#define SLCCTRL_SW_RESET (1 << 2) /* Reset the NAND controller bit */
#define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
#define SLCCTRL_DMA_START (1 << 0) /* Start DMA channel bit */
/**********************************************************************
* slc_cfg register definitions
**********************************************************************/
#define SLCCFG_CE_LOW (1 << 5) /* Force CE low bit */
#define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
#define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
#define SLCCFG_DMA_BURST (1 << 2) /* DMA burst bit */
#define SLCCFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
#define SLCCFG_WIDTH (1 << 0) /* External device width, 0=8bit */
/**********************************************************************
* slc_stat register definitions
**********************************************************************/
#define SLCSTAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
#define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
#define SLCSTAT_NAND_READY (1 << 0) /* NAND device is ready bit */
/**********************************************************************
* slc_int_stat, slc_ien, slc_isr, and slc_icr register definitions
**********************************************************************/
#define SLCSTAT_INT_TC (1 << 1) /* Transfer count bit */
#define SLCSTAT_INT_RDY_EN (1 << 0) /* Ready interrupt bit */
/**********************************************************************
* slc_tac register definitions
**********************************************************************/
/* Clock setting for RDY write sample wait time in 2*n clocks */
#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
/* Write pulse width in clock cycles, 1 to 16 clocks */
#define SLCTAC_WWIDTH(n) (((n) & 0xF) << 24)
/* Write hold time of control and data signals, 1 to 16 clocks */
#define SLCTAC_WHOLD(n) (((n) & 0xF) << 20)
/* Write setup time of control and data signals, 1 to 16 clocks */
#define SLCTAC_WSETUP(n) (((n) & 0xF) << 16)
/* Clock setting for RDY read sample wait time in 2*n clocks */
#define SLCTAC_RDR(n) (((n) & 0xF) << 12)
/* Read pulse width in clock cycles, 1 to 16 clocks */
#define SLCTAC_RWIDTH(n) (((n) & 0xF) << 8)
/* Read hold time of control and data signals, 1 to 16 clocks */
#define SLCTAC_RHOLD(n) (((n) & 0xF) << 4)
/* Read setup time of control and data signals, 1 to 16 clocks */
#define SLCTAC_RSETUP(n) (((n) & 0xF) << 0)
/**********************************************************************
* slc_ecc register definitions
**********************************************************************/
/* ECC line party fetch macro */
#define SLCECC_TO_LINEPAR(n) (((n) >> 6) & 0x7FFF)
#define SLCECC_TO_COLPAR(n) ((n) & 0x3F)
/*
* DMA requires storage space for the DMA local buffer and the hardware ECC
* storage area. The DMA local buffer is only used if DMA mapping fails
* during runtime.
*/
#define LPC32XX_DMA_DATA_SIZE 4096
#define LPC32XX_ECC_SAVE_SIZE ((4096 / 256) * 4)
/* Number of bytes used for ECC stored in NAND per 256 bytes */
#define LPC32XX_SLC_DEV_ECC_BYTES 3
/*
* If the NAND base clock frequency can't be fetched, this frequency will be
* used instead as the base. This rate is used to setup the timing registers
* used for NAND accesses.
*/
#define LPC32XX_DEF_BUS_RATE 133250000
/* Milliseconds for DMA FIFO timeout (unlikely anyway) */
#define LPC32XX_DMA_TIMEOUT 100
/*
* NAND ECC Layout for small page NAND devices
* Note: For large and huge page devices, the default layouts are used
*/
static struct nand_ecclayout lpc32xx_nand_oob_16 = {
.eccbytes = 6,
.eccpos = {10, 11, 12, 13, 14, 15},
.oobfree = {
{ .offset = 0, .length = 4 },
{ .offset = 6, .length = 4 },
},
};
static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
/*
* Small page FLASH BBT descriptors, marker at offset 0, version at offset 6
* Note: Large page devices used the default layout
*/
static struct nand_bbt_descr bbt_smallpage_main_descr = {
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
.offs = 0,
.len = 4,
.veroffs = 6,
.maxblocks = 4,
.pattern = bbt_pattern
};
static struct nand_bbt_descr bbt_smallpage_mirror_descr = {
.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
| NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
.offs = 0,
.len = 4,
.veroffs = 6,
.maxblocks = 4,
.pattern = mirror_pattern
};
/*
* NAND platform configuration structure
*/
struct lpc32xx_nand_cfg_slc {
uint32_t wdr_clks;
uint32_t wwidth;
uint32_t whold;
uint32_t wsetup;
uint32_t rdr_clks;
uint32_t rwidth;
uint32_t rhold;
uint32_t rsetup;
bool use_bbt;
int wp_gpio;
struct mtd_partition *parts;
unsigned num_parts;
};
struct lpc32xx_nand_host {
struct nand_chip nand_chip;
struct lpc32xx_slc_platform_data *pdata;
struct clk *clk;
struct mtd_info mtd;
void __iomem *io_base;
struct lpc32xx_nand_cfg_slc *ncfg;
struct completion comp;
struct dma_chan *dma_chan;
uint32_t dma_buf_len;
struct dma_slave_config dma_slave_config;
struct scatterlist sgl;
/*
* DMA and CPU addresses of ECC work area and data buffer
*/
uint32_t *ecc_buf;
uint8_t *data_buf;
dma_addr_t io_base_dma;
};
static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
{
uint32_t clkrate, tmp;
/* Reset SLC controller */
writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
udelay(1000);
/* Basic setup */
writel(0, SLC_CFG(host->io_base));
writel(0, SLC_IEN(host->io_base));
writel((SLCSTAT_INT_TC | SLCSTAT_INT_RDY_EN),
SLC_ICR(host->io_base));
/* Get base clock for SLC block */
clkrate = clk_get_rate(host->clk);
if (clkrate == 0)
clkrate = LPC32XX_DEF_BUS_RATE;
/* Compute clock setup values */
tmp = SLCTAC_WDR(host->ncfg->wdr_clks) |
