SMBus.rar_c8051f410_visual c

//----------------------------------------------------------------------------- // F41x_SMBus_EEPROM.c //----------------------------------------------------------------------------- // Copyright 2006 Silicon Laboratories, Inc. // http://www.silabs.com // // Program Description: // // This example demonstrates how the C8051F41x SMBus interface can communicate // with a 256 byte I2C Serial EEPROM (Microchip 24LC02B). // - Interrupt-driven SMBus implementation // - Only master states defined (no slave or arbitration) // - Timer1 used as SMBus clock source // - Timer3 used by SMBus for SCL low timeout detection // - SCL frequency defined by <SMB_FREQUENCY> constant // - Pinout: // P0.0 -> SDA (SMBus) // P0.1 -> SCL (SMBus) // // P2.1 -> LED // // P2.7 -> C2D (debug interface) // // all other port pins unused // // How To Test: // // 1) Download code to a 'F41x device that is connected to a 24LC02B serial // EEPROM (see the EEPROM datasheet for the pinout information). // 2) Run the code: // a) the test will indicate proper communication with the EEPROM by // turning on the LED at the end the end of the test // b) the test can also be verified by running to the if statements // in main and checking the sent and received values by adding // the variables to the Watch Window // // NOTE: On the 'F410 Target Board, verify J13 and J14 are not populated // before testing. // // FID: 41X000025 // Target: C8051F41x // Tool chain: Raisonance / Keil // Command Line: None // // Release 1.1 / 11 MAR 2010 (GP) // -Tested with Raisonance // // Release 1.0 // -Initial Revision (TP) // -30 MAR 2006 // //----------------------------------------------------------------------------- // Includes and Device-Specific Parameters //----------------------------------------------------------------------------- #include <compiler_defs.h> #include <C8051F410_defs.h> //----------------------------------------------------------------------------- // Global CONSTANTS //----------------------------------------------------------------------------- #define SYSCLK 24500000 // System clock frequency in Hz #define SMB_FREQUENCY 50000 // Target SCL clock rate // This example supports between 10kHz // and 100kHz #define WRITE 0x00 // SMBus WRITE command #define READ 0x01 // SMBus READ command // Device addresses (7 bits, lsb is a don't care) #define EEPROM_ADDR 0xA0 // Device address for slave target // Note: This address is specified // in the Microchip 24LC02B // datasheet. // SMBus Buffer Size #define SMB_BUFF_SIZE 0x08 // Defines the maximum number of bytes // that can be sent or received in a // single transfer // Status vector - top 4 bits only #define SMB_MTSTA 0xE0 // (MT) start transmitted #define SMB_MTDB 0xC0 // (MT) data byte transmitted #define SMB_MRDB 0x80 // (MR) data byte received // End status vector definition //----------------------------------------------------------------------------- // Global VARIABLES //----------------------------------------------------------------------------- unsigned char* pSMB_DATA_IN; // Global pointer for SMBus data // All receive data is written here unsigned char SMB_SINGLEBYTE_OUT; // Global holder for single byte writes. unsigned char* pSMB_DATA_OUT; // Global pointer for SMBus data. // All transmit data is read from here unsigned char SMB_DATA_LEN; // Global holder for number of bytes // to send or receive in the current // SMBus transfer. unsigned char WORD_ADDR; // Global holder for the EEPROM word // address that will be accessed in // the next transfer unsigned char TARGET; // Target SMBus slave address bit SMB_BUSY = 0; // Software flag to indicate when the // EEPROM_ByteRead() or // EEPROM_ByteWrite() // functions have claimed the SMBus bit SMB_RW; // Software flag to indicate the // direction of the current transfer bit SMB_SENDWORDADDR; // When set, this flag causes the ISR // to send the 8-bit <WORD_ADDR> // after sending the slave address. bit SMB_RANDOMREAD; // When set, this flag causes the ISR // to send a START signal after sending // the word address. // For the 24LC02B EEPROM, a random read // (a read from a particular address in // memory) starts as a write then // changes to a read after the repeated // start is sent. The ISR handles this // switchover if the <SMB_RANDOMREAD> // bit is set. bit SMB_ACKPOLL; // When set, this flag causes the ISR // to send a repeated START until the // slave has acknowledged its address sbit LED = P2^1; // LED on port P2.1 sbit SDA = P0^0; // SMBus on P0.0 sbit SCL = P0^1; // and P0.1 //----------------------------------------------------------------------------- // Function PROTOTYPES //----------------------------------------------------------------------------- void SMBus_Init(void); void Timer1_Init(void); void Timer3_Init(void); void Port_Init(void); void SMBus_ISR(void); void Timer3_ISR(void); void EEPROM_ByteWrite(unsigned char addr, unsigned char dat); void EEPROM_WriteArray(unsigned char dest_addr, unsigned char* src_addr, unsigned char len); unsigned char EEPROM_ByteRead(unsigned char addr); void EEPROM_ReadArray(unsigned char* dest_addr, unsigned char src_addr, unsigned char len); //----------------------------------------------------------------------------- // MAIN Routine //----------------------------------------------------------------------------- // // Main routine performs all configuration tasks, then loops forever sending // and receiving SMBus data to the slave EEPROM. void main (void) { char in_buff[8] = {0}; // Incoming data buffer char out_buff[8] = "ABCDEFG"; // Outgoing data buffer unsigned char temp_char; // Temporary variable bit error_flag = 0; // Flag for checking EEPROM contents unsigned char i; // Temporary counter variable PCA0MD &= ~0x40; // WDTE = 0 (disable watchdog timer) OSCICN |= 0x07; // Set internal oscillator to highest // setting of 24500000 // If slave is holding SDA low because of an improper SMBus res