JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
DECEMBER 2011
JEDEC
STANDARD
Wide I/O Single Data Rate
JESD229
(Wide I/O SDR)
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JEDEC Standard No. 229
Page 1
WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)
(From JEDEC Board Ballot JCB-11-79, formulated under the cognizance of the JC-42.6 Subcommittee on Low
Power Memories.)
1Scope
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics,
packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The
purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb
SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1
to 4 memory devices and a controller device. This standard was created using aspects of the following standards:
DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Each aspect of the
standard was considered and approved by committee ballot(s). The accumulation of these ballots was then
incorporated to prepare the Wide I/O standard.
2 General Description
2.1 Terms and Definitions
Within the Wide I/O standard, these terms have particular meanings:
Stack: All memory chips in the memory system taken together in one assembly.
NOTE This Wide I/O standard supports memory stacks that include up to 4 memory chips.
Slice: One memory chip in the stack of memory chips.
Rank: That portion of memory from one memory die that is logically connected to a single channel within the
memory stack.
Channel: Both a set of physically discrete connections within the Wide I/O interface and a logically discrete,
independently controlled partition of the Wide I/O interface.
NOTE The Wide I/O interface supports 4 physical and 4 logical channels. Each physical channel contains all the control, data
and clock signals necessary to independently control each of the 4 logical channels in the Wide I/O interface. Aside from a few
global configuration options, each logical channel has its own set of mode registers, can have different DRAM pages open, can be
independently clocked and can even be in different power states. The physical channel also contains power and ground signals but
all power and ground signals on all physical channels must be at their appropriate levels for any portion of the Wide I/O device to
operate correctly. The physical channel also contains a reset signal but the Wide I/O interface defines reset to be per slice rather
than per channel.
2.2 Micropillar-out
2.2.1 Key Features
- 128 Data Bits per channel
- Support for up to 32 Gbit monolithic density
- micropillars allocated for differential CK/DQS for future DDR extension
- 5 Serial Scan connections/channel + 1 overall serial enable
- Per byte write masks
- 1 “must be routed through substrate” Direct Access micropillar per channel
- 2 missing row vertical channel spacing, 6 missing column horizontal channel spacing
- Power micropillar count supports current requirements of low-power memory space