序列检测器1100100
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MEALY IS
PORT ( CLK,DATAIN,RESET:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END MEALY;
ARCHITECTURE BEHAV OF MEALY IS
TYPE STATES IS(ST0,ST1,ST2,ST3,ST4,ST5,ST6);
SIGNAL STX:STATES;
BEGIN
COMREG:PROCESS(CLK,RESET) BEGIN
IF RESET='1'THEN STX<=ST0;
ELSIF CLK'EVENT AND CLK='1'THEN CASE STX IS
WHEN ST0=>IF DATAIN='1'THEN STX<=ST1;END IF;
WHEN ST1=>IF DATAIN='1'THEN STX<=ST2;END IF;
WHEN ST2=>IF DATAIN='0'THEN STX<=ST3;END IF;
WHEN ST3=>IF DATAIN='0'THEN STX<=ST4;END IF;
WHEN ST4=>IF DATAIN='1'THEN STX<=ST5;END IF;
WHEN ST5=>IF DATAIN='0'THEN STX<=ST6;END IF;
WHEN ST6=>IF DATAIN='0'THEN STX<=ST0;END IF;
END CASE;
END IF;
END PROCESS COMREG;
COM1:PROCESS(STX,DATAIN)BEGIN
CASE STX IS
WHEN ST0=>IF DATAIN='1'THEN Q<="0000001";
ELSE Q<="0000000";END IF;
WHEN ST1=>IF DATAIN='1'THEN Q<="0000011";
ELSE Q<="0000001";END IF;
WHEN ST2=>IF DATAIN='0'THEN Q<="0000110";
ELSE Q<="0000001";END IF;
WHEN ST3=>IF DATAIN='0'THEN Q<="0001100";
ELSE Q<="0000001";END IF;
WHEN ST4=>IF DATAIN='1'THEN Q<="0011001";
ELSE Q<="0000000";END IF;
WHEN ST5=>IF DATAIN='0'THEN Q<="0110010";
ELSE Q<="0000001";END IF;
WHEN ST6=>IF DATAIN='0'THEN Q<="0000000";
ELSE Q<="0000001";END IF;
WHEN OTHERS=>Q<="0000000";
END CASE ;
END PROCESS COM1;
END BEHAV;
60进制加法器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT60 IS
PORT (CLK,RST,EN :IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
COUT:OUT STD_LOGIC);
END CNT60;
ARCHITECTURE BEHAV OF CNT60 IS
BEGIN
PROCESS(CLK,RST,EN)
VARIABLE CQI:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF RST='1' THEN CQI:=(OTHERS=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
IF EN ='1' THEN
IF CQI <"00111011" THEN CQI:=CQI+1;
ELSE CQI:=(OTHERS=>'0');END IF;
END IF;
END IF;
IF CQI="00111011" THEN COUT <= '1';
ELSE COUT <= '0';END IF;
CQ<=CQI;
END PROCESS;
END BEHAV;
