时钟发生器的 VHDL 实现程序如下:
`timescale 1ns/10ps
Module cpu_CLKGE(fetch,clk2,clk,alu_clk);
Output fetch, clk2,clk,alu_clk;
Reg fetch,clk2,clk;
Parameter period=60;
Assign alu_clk=(fetch|clk2|clk);
Initial
Fork
Clk=0;
Clk2=1;
Fetch=1;
Forever #(period/2) clk=-clk;
Forever #(period) clk2=-clk2;
Forever #(2*period) fetch=-fetch;
Join
Endmodule